National Instruments PXIe-4357, Руководство пользователя

Страница: 18 / 28

2-10 | ni.com
Chapter 2 Using the NI PXIe-4357
NI PXIe-4357 Block Diagram
Figure 2-4 shows the NI PXIe-4357 block diagram.
Figure 2-4. NI PXIe-4357 Block Diagram
Sample Rates
This section explains timing on the NI PXIe-4357.
Hardware and Software Timing
You can use software timing or hardware timing to control when a signal is acquired. With
hardware timing, a digital signal, such as the sample clock on the NI PXIe-4357, controls the
acquisition rate. With software timing, the acquisition rate is determined by the software and
operating system instead of by the measurement device. A hardware clock can run faster than a
software loop. A hardware clock can sample data with less jitter in the data rate than a software
loop.
AI0
AI5
AI10
AI15
M u ltiplexer
Acce ss ory
ADC0
PXIe
B us
Interf a ce
PXIe B
us
Digit a l
I s ol a tor s
Bo a rd
Firmw a re
(FLA S H)
FPGA
AI1
AI6
AI11
AI16
M u ltiplexer ADC1
AI2
AI7
AI12
AI17
M u ltiplexer
ADC2
AI 3
AI8
AI1 3
AI18
M u ltiplexer ADC 3
AI4
AI9
AI14
AI19
M u ltiplexer ADC4