National Instruments PXI Express NI PXIe-1073, Руководство пользователя, Страница: 15 / 42

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PXIe-1073 User Manual
PXI Local Bus
The PXI backplane local bus is a daisy-chained bus that connects each peripheral slot with the
adjacent peripheral slots to the left and right (refer to Figure 1-5).
The backplane routes PXI Local Bus 6 between adjacent PXI slots. The left local bus 6 from slot
2 is not routed anywhere and the right local bus signal from slot 6 is not routed anywhere.
Local bus signals may range from high-speed TTL signals to analog signals as high as 42 V.
Figure 1-5.
Local Bus Routing
PXI Trigger Bus
All slots share eight PXI trigger lines. You can use these trigger lines in a variety of ways. For
example, you can use triggers to synchronize the operation of several different PXI peripheral
modules. Modules can pass triggers to one another, allowing precisely timed responses to
asynchronous external events the system is monitoring or controlling.
The PXI trigger lines allow you to send trigger signals to, and receive trigger signals from, every
slot in the chassis. Static trigger routing (user-specified line assignments) can be configured
through Measurement & Automation Explorer (MAX). Dynamic routing of triggers (automatic
line assignments) is supported through certain National Instruments drivers like NI-DAQmx.
System Reference Clock
The PXIe-1073 provides a 10 MHz clock (PXI_CLK10) and 100 MHz clock (PXIe_CLK100)
to each peripheral slot. The 100 MHz clock is a high speed LVPECL clock, while the 10 MHz
clock is a TTL/CMOS clock. The backplane also provides a PXIe_SYNC100 signal which
asserts a 10 ns pulse which is synchronous to PXIe_CLK100.
P
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al Slot [2]
P
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al Slot [3]
P
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al Slot [4]
Local
Bus
Local
Bus
PCI Arbitration and Clock Signals
P
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al Slot [5]
P
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al Slot [6]
Local
Bus
Local
Bus
Embedded
MXI
Controller