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Appendix A
Specifications
A-2
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National Instruments Corporation
External Connections
Trigger sense...........................................TTL
Trigger level ...........................................Programmable (rising or falling)
CSYNC sense .........................................TTL
CSYNC level ..........................................Programmable (rising or falling)
Minimum pulse width.............................50 ns
V
IH
(TTL) ...............................................2 V
V
IL
(TTL)................................................0.8 V
Internal Pixel Clock
Generated frequency...............................11.66 to 15.78 MHz
Aspect correction for
standard video sources............................–5% to +7%
Pixel jitter ...............................................< 5 ns peak
PCI Interface
PCI initiator (master) capability .............Supported
PCI target (slave) capability ...................Supported
Data path.................................................32 bits
Card voltage............................................5 V only
Card type.................................................32-bit half-size card
Parity generation/checking,
error reporting.........................................Supported
Target decode speed ...............................Medium (1 clock)
Target fast back-to-back capability ........Supported
Resource locking ....................................Supported as a master and slave
PCI interrupts..........................................Interrupts passed on
INTA# signal