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PXI Trigger Bus
All slots share eight trigger lines.You can use these trigger lines in a variety of ways. For
example, you can use triggers to synchronize the operation of several different PXI peripheral
modules. In other applications, one module can control carefully timed sequences of operations
performed on other modules in the system. Modules can pass triggers to one another, allowing
precisely timed responses to asynchronous external events the system is monitoring or
controlling.
System Reference Clock
The PXIe-1078 chassis supplies PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 to every
peripheral slot with an independent driver for each signal.
An independent buffer (having a source impedance matched to the backplane and a skew of less
than 500 ps between slots) drives PXI_CLK10 to each peripheral slot. You can use this common
reference clock signal to synchronize multiple modules in a measurement or control system.
An independent buffer drives PXIe_CLK100 to each peripheral slot. These clocks are matched
in skew to less than 100 ps. The differential pair must be terminated on the peripheral with
LVPECL termination for the buffer to drive PXIe_CLK100 so that when there is no peripheral
or a peripheral that does not connect to PXIe_CLK100, there is no clock being driven on the pair
to that slot.
An independent buffer drives PXIe_SYNC100 to each peripheral slot. The differential pair must
be terminated on the peripheral with LVPECL termination for the buffer to drive
PXIe_SYNC100 so that when there is no peripheral or a peripheral that does not connect to
PXIe_SYNC100, there is no clock being driven on the pair to that slot.
PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 have the default timing relationship
described in Figure 1-6.
Figure 1-6.
System Reference Clock Default Behavior
PXIe_CLK100
PXI_CLK10
PXIe_
S
YNC100
0 1 2
3
4 5 6 7
8
9 0 1 2
3
4 5 6 7
8
9 0 1 2
3
4 5 6 7
8
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PXIe1078UM.book Page 9 Monday, December 23, 2019 10:44 AM
