2-12
|
ni.com
Chapter 2
Digital I/O
For example, if the FIFO contains five samples, the pattern generated consists of sample #1, #2,
#3, #4, #5, #1, #2, #3, #4, #5, #1, and so on.
The following DO (waveform generation) timing signals are featured:
•
•
DO Sample Clock Timebase Signal
•
•
Signals with an * support digital filtering. Refer to the
, for
more information.
DO Sample Clock Signal
The device uses the DO Sample Clock (do/SampleClock) signal to update the DO terminals with
the next sample from the DO waveform generation FIFO. If the device receives a DO Sample
Clock when the FIFO is empty, it reports an underflow error to the host software.
By default, the NI 6614 routes the divided down DO Sample Clock Timebase to DO Sample
Clock. You can route many other signals to DO Sample Clock. To view the complete list of
possible routes, see the
Device Routes
tab in MAX. Refer to
Device Routing in MAX
in the
NI-DAQmx Help
or the
LabVIEW Help
for more information.
Routing DO Sample Clock to an Output Terminal
DO Sample Clock can be routed out to any PFI <0..39>, PXI_Trig <0..7>, or PXIe-DSTARC
terminal.
Other Timing Requirements
The DO timing engine internally generates DO Sample Clock unless configured to an external
source. DO Start Trigger starts the timing engine and either the software or hardware can stop it
once a finite generation completes. When using the DO timing engine, a configurable delay can
be configured from DO Start Trigger to the first DO Sample Clock pulse. By default, this delay
is two ticks of DO Sample Clock Timebase. Figure 2-8 shows the relationship of DO Sample
Clock to DO Start Trigger.
