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Chapter 2
Device Overview
©
National Instruments Corporation
2-3
This feat
u
re is
u
sef
u
l in applications with two or more co
u
nters that are
armed by an external start trigger, or that
u
se the same PFI line as a co
u
nter
control signal. Pad synchronization is only
u
sef
u
l if the co
u
nters involved
are
u
sing one of the internal timebases. A co
u
nter is
u
sing maxim
u
m
timebase as its so
u
rce if the synchrono
u
s co
u
nting mode is enabled for
that co
u
nter.
Fig
u
u
strate how pad synchronization can be
u
sef
u
l.
These fig
u
res ass
u
me a 0.5 and a 0.75 SOURCE cycle delay between the
PFI 38 inp
u
t pin, and CTR 0 GATE and CTR 1 GATE, respectively.
Fig
u
re 2-2 shows co
u
nter 0 at the gate edge on PFI 38 one so
u
rce period
before co
u
nter 1. Fig
u
re 2-3 shows both co
u
nters at the gate edge on PFI 38
at the same time.
Figure 2-2.
Counter 0 at Gate Edge on PFI 38 One Source Period before Counter 1
Counter
Source
PFI 38
at CTR 0 GATE
PFI 38
at CTR 1 GATE
Sampled
GATE at Ctr0
Sampled
GATE at Ctr1
1/2 Cycles
1/4 Cycle
PFI 38
at Input To ASIC