Signal Name
Pin(s)
Signal
Type
Signal Description
DIO<0..15>-
15, 18, 21, 24, 27, 30, 33,
36, 39, 42, 45, 48, 51, 54,
57, 60
Data
Negative differential terminal for the
bidirectional digitial I/O data channels 0
through 15.
PFI <1..4>+
2, 5, 8, 11
Control
Positive differential terminals for
bidirectional PFI channels 1 through 4.
PFI <1..4>-
3, 6, 9, 12
Control
Negative differential terminals for
bidirectional PFI channels 1 through 4.
SE_PFI<1..3> 68, 71, 72
Control
Single-ended terminals for bidirectional PFI
channels 1 through 3.
GND
1, 4, 7, 10, 13, 16, 19, 22,
25, 28, 31, 34, 37, 40, 42,
46, 49, 52, 55, 58, 69
Ground
Ground reference for signals.
Table 3. NI 6589 DDC Connector Names and Descriptions
For more detailed information about the NI 6589 front panel connectors, refer to the
NI 6589 Specifications.
Block Diagrams
The following figures show the data flow through the NI 6589. Single-ended data
lines use standard clock levels to interpret data as either a binary zero or a one in
high-speed digital data transfers. Differential data lines provide a low-noise, low-
power, low-amplitude differential method for high-speed digital data transfer.
Figure 4. Clock Input Signal
CLOCK IN
Global Clock to
NI FlexRIO FPGA Module
(UserGclkLvttl)
© National Instruments
13
NI-6589
Содержание NI-6589
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