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NI 6584R User Guide and Specifications

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Creating an FPGA Target VI

In the

Project Explorer

window, right-click

My Computer

and select

New»Targets and

Devices

In the

Add Targets and Devices on My Computer

window, select the

Existing Target or Device

radio button and expand the FPGA Target. The target is displayed.

Select your device and click

. The target and target properties are loaded into the project tree.

In the

Project Explorer

window, right-click the FPGA target and select

New»VI

. A blank VI

opens.

Select Window

Show»Block Diagram

to open the block diagram window.

In the

Project Explorer

window, select

FPGA Target (RIO

, PXI-79

Right-click

IO Module

and select

Properties

. In the General category, you can see the available

component-level IP (CLIP) for the NI 6584 in the Component Level IP pane. If the category
information is dimmed, select the

Enable IO Module

checkbox.

Note

For more information about CLIP for the NI 6584, refer to the

NI 6584 Component-Level

Intellectual Property

section of this document.

Select

NI 6584 Full-Duplex

to configure the software for the full duplex version of the NI 6584R.

Select

NI 6584 Basic Connector

to use the connector-based CLIP. Click

10. In the

Project Explorer

window, select

IO Module (NI 6584 Full-Duplex : NI 6584 Basic

Connector)

11. Select

, and

TX_Enable

and drag them onto the block diagram.

12. Add a While Loop around the three Data nodes.

13. Wire an indicator from the output of the

IO Module\RX

14. Wire a control to the input of the

IO Module\TX

15. Wire a numeric constant to the input of the

IO Module\TX_Enable

node. Set the value to 65,535.

(This enables all 16 TX channels like

0xFFFF

in hexadecimal.)

16. Wire a False constant to the stop condition of the While Loop.

Your block diagram should now resemble the block diagram in Figure 6.

Figure 6.

Data RW (FPGA).vi Block Diagram

17. Save the VI as

Data RW (FPGA).vi

18. Close the VI.

19. In the Project Explorer window under

My Computer

, expand the tree view for your device,

right-click

Data RW (FPGA).vi

and select

Compile

to compile the files for your target.

Содержание NI 6584R

Страница 1: ...NI 6584 ...

Страница 2: ...n or generation on the same pin The unterminated versions of the full and half duplex devices are useful in multi drop situations when you are already using a terminated bus and the terminated devices are useful in high speed point to point situations or as the terminated end points on a multi drop bus Contents Connecting Signals 2 Front Panel 2 Cables 4 FPGA 6 Using Your NI 6584R with a LabVIEW F...

Страница 3: ...oth terminated and unterminated devices Figure 2 NI 6584 Connector 0 Pin Assignments Full Duplex 68 34 67 33 66 32 65 31 64 30 63 29 62 28 61 27 60 26 59 25 58 24 57 23 56 22 55 21 54 20 53 19 52 18 51 17 50 16 49 15 48 14 47 13 46 12 45 11 44 10 43 9 42 8 41 7 40 6 39 5 38 4 37 3 36 2 35 1 Connector 0 Ports 0 8 TX_6 TX_7 RX_7 RX_6 TX_7 RX_6 TX_6 RX_7 GND TX_4 TX_5 RX_5 RX_4 TX_5 RX_4 TX_4 RX_5 TX...

Страница 4: ...assis NI is not liable for any damage resulting from such signal connections For the maximum input and output ratings for each signal refer to the Specifications section of this document 68 34 67 33 66 32 65 31 64 30 63 29 62 28 61 27 60 26 59 25 58 24 57 23 56 22 55 21 54 20 53 19 52 18 51 17 50 16 49 15 48 14 47 13 46 12 45 11 44 10 43 9 42 8 41 7 40 6 39 5 38 4 37 3 36 2 35 1 Connector 0 Ports ...

Страница 5: ...CI to Eight DB9 cable 197546 01 connected to the NI 6584 at Connector 0 Ports 1 8 and then fanning out to display each of its eight nine pin port connectors Figure 4 NI 6584 and NI VHDCI to Eight DB9 Cable 1 NI 6584 adapter module 2 NI VHDCI to Eight DB9 cable 197546 01 PORT 1 1 2 ...

Страница 6: ...6 RX_1 RX_3 RX_5 RX_7 RX_9 RX_11 RX_13 RX_15 7 TX_1 TX_3 TX_5 TX_7 TX_9 TX_11 TX_13 TX_15 8 TX_0 TX_2 TX_4 TX_6 TX_8 TX_10 TX_12 TX_14 9 TX_0 TX_2 TX_4 TX_6 TX_8 TX_10 TX_12 TX_14 GND Ground Table 2 Pin Assignments on Each Port Half Duplex Connector Pin Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 1 GND GND GND GND GND GND GND GND 2 NC NC NC NC NC NC NC NC 3 TX_1 RX_1 TX_3 RX_3 TX_5 RX_...

Страница 7: ... GPIO_21 1 GPIO_1 0 GCLK_SE GPIO_18 1 Channel 1 GPIO_22 1 GPIO_14 0 GPIO_7_CC 0 GPIO_14_n 0 Channel 2 GPIO_8 0 GPIO_12 0 GPIO_23_CC 1 GPIO_27 1 Channel 3 GPIO_9 0 GPIO_13 0 GPIO_24_CC 1 GPIO_29 1 Channel 4 GPIO_54 3 GPIO_60 3 GPIO_39_CC 2 GPIO_61 3 Channel 5 GPIO_43 2 GPIO_47 2 GPIO_40_CC 2 GPIO_65 3 Channel 6 GPIO_52 3 GPIO_51 3 GPIO_37_CC 2 GPIO_35 2 Channel 7 GPIO_53 3 GPIO_63 3 GPIO_38_CC 2 GP...

Страница 8: ...VHDCI to Eight DB9 cable to the DUT with proper termination Note This exercise shows how to complete these tasks for the full duplex version of the NI 6584 To complete these tasks with a different hardware version of the NI 6584 replace every instance of Full Duplex in these instructions with Half Duplex Full Duplex No Termination or Half Duplex No Termination depending on which device you are usi...

Страница 9: ... On the front panel complete the following steps to acquire data a Set the Acq Data Width control to a number between 1 and 32 The default is 8 b Set the Samples to Acquire control to a number between 1 and 1 023 The default is 5 c Set the Acq Clock Divider The default acquisition rate of the UART is 16 Mbit s but it is capable of running at any integer division of this rate For example to acquire...

Страница 10: ...6584R This exercise also demonstrates how to compile the FPGA VI on your target and run a VI on the host machine This exercise shows how to complete these tasks for the full duplex version of the NI 6584 To complete these tasks with a different hardware version of the NI 6584 replace every instance of Full Duplex in these instructions with Half Duplex Full Duplex No Termination or Half Duplex No T...

Страница 11: ... the NI 6584 refer to the NI 6584 Component Level Intellectual Property section of this document 8 Select NI 6584 Full Duplex to configure the software for the full duplex version of the NI 6584R 9 Select NI 6584 Basic Connector to use the connector based CLIP Click OK 10 In the Project Explorer window select IO Module NI 6584 Full Duplex NI 6584 Basic Connector 11 Select RX TX and TX_Enable and d...

Страница 12: ...ame appears under the Open FPGA VI Reference function on the block diagram 8 Add a While Loop to the block diagram with a control on the loop condition 9 Add the Read Write Control function from the FPGA Interface palette inside the While Loop 10 Wire the Open FPGA VI Reference function FPGA VI Reference Out indicator to the FPGA VI Reference In control on the Read Write Control function 11 Wire t...

Страница 13: ...dule RX indicator returns the number 65 535 because all RX lines are floating 4 Click the Stop button on the front panel and close the VI NI 6584 Component Level Intellectual Property The LabVIEW FPGA Module includes a feature for HDL IP integration called CLIP NI FlexRIO devices support two types of CLIP user defined and socketed User defined CLIP allows users to insert HDL IP into an FPGA target...

Страница 14: ...inversion NI 6584 Basic Connector Provides read write access to all RS 485 422 channels on Connector 0 Ports 1 8 The individual data lines for each connector are accessed using a U16 data type in LabVIEW FPGA Each output line has a write enable signal Each input line is always enabled This CLIP provides a clock signal for import or export on the BNC CLOCK connector This CLIP also allows for indivi...

Страница 15: ...elp1 Embedded in LabVIEW Help Contains information about the basic functionality of LabVIEW FPGA Module NI FlexRIO Help1 Embedded in LabVIEW FPGA Module Help Contains FPGA module adapter module and CLIP configuration information LabVIEW Examples Available in LabVIEW Example Finder Contains examples of how to run FPGA VIs and Host VIs on your device Other Useful Information on ni com ni com ipnet C...

Страница 16: ...bus Figures 10 and 11 show the block diagrams for the full and half duplex versions of the NI 6584 Figure 10 NI 6584 Block Diagram Full Duplex Figure 11 NI 6584 Block Diagram Half Duplex Note The VHDCI connector shown in the preceding figures is labeled CONNECTOR 0 Ports 1 8 on the front panel of the NI 6584 1 Terminated devices 199496 01 199496 02 have 100 Ω termination Unterminated devices 19949...

Страница 17: ...voltage 100 µA load High Minimum 3 0 V Low Maximum 0 1 V Power Power requirements from the NI FlexRIO FPGA module 12 V 100 mA 1 2 W max 3 3 V 500 mA 1 65 W max Physical Dimensions 13 1 2 0 12 9 cm 5 2 0 8 5 1 in Weight 298 g 10 5 oz Front panel connectors Two BNC connectors and one 68 pin VHDCI connector Environmental The NI 6584 is intended for indoor use only Operating environment 0 C to 55 C te...

Страница 18: ...or UL and other safety certifications refer to the product label or the Online Product Certification section Electromagnetic Compatibility This product meets the requirements of the following EMC standards for electrical equipment for measurement control and laboratory use EN 61326 1 IEC 61326 1 Class A emissions Basic immunity EN 55011 CISPR 11 Group 1 Class A emissions AS NZS CISPR 11 Group 1 Cl...

Страница 19: ...e headquarters is located at 11500 North Mopac Expressway Austin Texas 78759 3504 National Instruments also has offices located around the world to help address your support needs For telephone support in the United States create your service request at ni com support and follow the calling instructions or dial 512 795 8248 For telephone support outside the United States contact your local branch ...

Страница 20: ...nstruments trademarks Other product and company names mentioned herein are trademarks or trade names of their respective companies For patents covering National Instruments products technology refer to the appropriate location Help Patents in your software the patents txt file on your media or the National Instruments Patent Notice at ni com patents 2010 National Instruments Corporation All rights...

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