© National Instruments
|
1-5
Figure 1-9.
NI 651
8
Block Diagram
Figure 1-10.
NI 6519 Block Diagram
VCC
P<2..
3
>.<0..7>
OUT.COM (GND)
16
PCI B
us
D
a
t
a
/Control
PCI B
us
Interf
a
ce
D
a
t
a
/Control
Fl
as
h
Memory
Config
u
r
a
tion
Control
10 MHz
Clock
Ind
us
tri
a
l Digit
a
l
I/O Control FPGA
DIO Line
s
Progr
a
mm
ab
le
Power-Up
S
t
a
te
s
W
a
tchdog Timer
Ch
a
nge
Detection
Digit
a
l
Filtering
I/O Connector
16
IN.COM
P<0..1>.<0..7>
VCC
x16 B
a
nk I
s
ol
a
ted
Inp
u
t Ch
a
nnel
s
DI
DO
x16 B
a
nk I
s
ol
a
ted
O
u
tp
u
t Ch
a
nnel
s
Volt
a
ge
Reg
u
l
a
tor
16
Digit
a
l
O
u
tp
u
t
s
16
Digit
a
l
Inp
u
t
s
I/O Connector
PCI B
us
D
a
t
a
/Control
PCI B
us
Interf
a
ce
10 MHz
Clock
16
IN.COM
P<1..2>.<0..7>
VCC
x16 B
a
nk I
s
ol
a
ted Inp
u
t Ch
a
nnel
s
DI
Ind
us
tri
a
l Digit
a
l
I/O Control FPGA
DIO Line
s
Progr
a
mm
ab
le
Power-Up
S
t
a
te
s
W
a
tchdog Timer
Ch
a
nge
Detection
Digit
a
l
Filtering
D
a
t
a
/Control
Fl
as
h
Memory
Config
u
r
a
tion
Control
OUT.COM (VCC)
P<2..
3
>.<0..7>
GND
DO
Volt
a
ge
Reg
u
l
a
tor
x16 B
a
nk I
s
ol
a
ted O
u
tp
u
t Ch
a
nnel
s
16
16
Digit
a
l
Inp
u
t
s
16
Digit
a
l
O
u
tp
u
t
s
