Chapter 1
Getting Started with Your NI 4472
1-6
ni.com
The CompactPCI specification permits vendors to develop sub-buses that
coexist with the basic PCI interface on the CompactPCI bus. Compatible
operation is not guaranteed between CompactPCI devices with different
sub-buses nor between CompactPCI devices with sub-buses and PXI.
The standard implementation for CompactPCI does not include these
sub-buses. Your NI 4472 for PXI/CompactPCI will work in any standard
CompactPCI chassis adhering to the
PICMG CompactPCI 2.0 R2.1
specification.
Caution
Damage to your equipment can occur if the lines shown in Table 1-1 are driven
by a CompactPCI sub-bus.
PXI-specific features are implemented on the J2 connector of the
CompactPCI bus. Table 1-1 lists the J2 pins used by your NI 4472 for
PXI/CompactPCI. Your PXI device is compatible with any CompactPCI
chassis with a sub-bus that does not drive these lines. Even if the sub-bus is
capable of driving these lines, the PXI device is still compatible as long as
those pins on the sub-bus are disabled by default and not ever enabled.
Damage may result if these lines are driven by the sub-bus.
In some circumstances, it is possible to drive some of these lines in the same
chassis as your NI 4472. For more information, search the
NI KnowledgeBase at
ni.com/public
.
Table 1-1.
J2 Connector Pins Used by the NI 4472 for PXI/CompactPCI
NI 4472 for
PXI/CompactPCI Signal
PXI Pin Name
PXI J2 Pin Number
Master Clock Distribution
LBL<0..12>
C20, E20, A19, C19, D19, E19, D15,
D2, E2, A1, C1, D1, E1
Sync Pulse
PXI Trigger 5
C18
Reserved
LBR<0..12>
A21, C21, D21, E21, A20, B20, E15,
A3, C3, D3, E3, A2, B2
Master Clock Reception
PXI Star In
D17