Chapter 3
Device Overview and Theory of Operation
3-16
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at exactly the same time. Figure 3-13 illustrates the oversample pulse trains
on two NI 447
X
devices sampling at 102.4 kS/s. In this example, there is a
delay between acquisition samples of five oversample intervals, or about
350 ns. This delay may be any value up to a whole sample interval, which
is about 10
µ
s at this acquisition rate.
Figure 3-13.
Sample Delay between NI 447
X
Modules After Receiving a Shared
Oversample Clock
The solution to the clock-delay issue is to configure the master device to
issue a SYNC pulse before the acquisition. The clock master sends a single
active low, or inverted, pulse on the RTSI 5/TRIG 5 line, the dedicated line
for the SYNC pulse. The ADCs in the clock master and clock slaves receive
this pulse nearly simultaneously. The SYNC pulse forces all the ADCs to a
reset state, emptying their digital filters and synchronizing their clock
dividers. After exiting the reset state, all NI 447
X
modules run at the same
frequency and have minimal phase difference between sample clocks.
Figure 3-14 illustrates how this technique minimizes the sample delay.
t
p
≈
70 ns
NI 4472 #1
NI 4472 #2
t
p
Sample Delay
≈
350 ns
Data Returned
Data Returned
