Chapter 3
Hardware Overview
3-20
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If CLKIN is 10 MHz, the NI PXIe-6672 can compensate for
distribution delays in the backplane. The feedback in the PLL comes
from PXI_CLK10. This PLL makes it possible for the NI PXIe-6672
to align clock edges at CLKIN with the edges of PXI_CLK10 that the
modules receive. If you split an external (accurate) 10 MHz reference
and route it to two chassis, they can both lock to it. The result is a
tighter synchronization of PXI_CLK10 on the chassis.