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Appendix B
Timing Signal Information
B-6
ni.com
Figures B-7 and B-8 show the input and output timing requirements
for AI SAMP CLK.
Figure B-7.
AI SAMP CLK Input Signal Timing
Figure B-8.
AI SAMP CLK Output Signal Timing
The AI CONV CLK pulses are masked off until the device generates
AI SAMP CLK. If you use internally generated conversions, the first
AI CONV CLK appears when the onboard SI2 counter reaches zero.
If you select an external AI CONV CLK, the first external pulse after
Ri
s
ing-Edge
Pol
a
rity
F
a
lling-Edge
Pol
a
rity
t
w
= 10 n
s
minimum
t
w
b.
S
c
a
n in Progre
ss
, Two Conver
s
ion
s
per
S
c
a
n
S
t
a
rt Pul
s
e
AI CONV REF
AI
S
AMP CLK
t
off
= 10 n
s
minimum
t
off
t
w
= 50 to 100 n
s
t
w
a
.
S
t
a
rt of
S
c
a
n
AI
S
AMP CLK