Theory of Operation
Chapter 6
GPIB-1014 User Manual
6-18
© National Instruments Corporation
DMA Requests. Internal or external requests activate the DMAC to transfer an operand. The
REQG bits of the OCR determine the manner in which requests are generated. Requests can be
externally generated by the device or internally generated by the DMAC using its internal
automatic request mechanism. Internal automatic requests can be generated at a maximum rate,
so that the channel always has a request pending, or at a limited rate, monitoring the bus
bandwidth use. Any of the two modes are used when performing memory-to-memory DMA
transfers. In GPIB-1014 GPIB applications, you must set the REQG bit to 10 to indicate that
external REQ line will initiate a transfer. After selecting external request generation mode, you
must also set the XRM bit in DCR to specify whether a channel must operate in cycle steal or
cycle steal with hold mode. Do not set XRM to 00 to select the burst transfer mode in the GPIB
DMA application. If internal request mode was chosen, the XRM bit can be ignored.
The GPIB-1014 uses cycle steal mode (with or without hold) for GPIB DMA data transfers. In
the cycle steal mode, the device (TLC) requests an operand transfer by generating a falling edge
on the REQ* line (REQ0* or REQ1*). The DMAC services the request by arbitrating for the
system bus and then driving the ACK* line active to transfer the operand. If the XRM bits
specify cycle steal without hold, the DMAC relinquishes the bus after each operand transfer. If
the XRM bits specify cycle steal with hold, the DMAC retains bus ownership for a short time
after an operand transfer in anticipation of a new request from the TLC within that time period.
If a new request is not present during the hold period, the DMAC relinquishes the bus by
unasserting its signal OWN*. The sample period is defined by the values programmed into the
GCR.
Data Transfers. All DMAC transfers are assumed to be between a 16-bit 68000 device (VMEbus
memory) and another device. By programming the DCR, the characteristics of the device can be
assigned. Each channel can communicate using the following protocols. For GPIB-1014 GPIB
DMA data transfers, you must set the device type to 10 for Device with ACK for both Channel 0
and Channel 1.
DTYP: Device Type
00 = 68000-compatible device – dual addressing
01 = 6800-compatible device – dual addressing
10 = Device with ACK – single addressing
11 = Device with ACK and READY – single addressing
Dual Address Transfers can be used with 68000-compatible (VMEbus memory) and
6800-compatible devices that must be explicitly addressed. Because the address bus is used to
address both the device and the memory, the data cannot be directly transferred to or from the
memory (the source) because the device (receiver) also requires addressing. Instead, the data is
transferred from the source to the DMAC and held in internal holding register(s). (This may take
more than one bus cycle.) After that, one or more transfers between the DMAC and the
destination are required to complete the operation.
Single Addressing Mode is used for implicitly addressed devices that do not require addressing
of the data register before the data can be transferred. Such peripherals use the acknowledge
(ACK) line to access the data register and require only one bus cycle to transfer the data between
themselves and memory. In case of a DMA write to a device, data is transferred directly from
the VMEbus memory into the device. Similarly, during a DMA read of a device, data from a
device is transferred directly into the VMEbus memory. In both cases, data is not temporarily
kept in the internal holding register(s) of the DMAC.
