National Instruments AT-MIO-64F-5, Руководство пользователя

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Chapter 3 Theory of Operation
© National Instruments Corporation 3-17 AT-MIO-64F-5 User Manual
Figure 3-12. Analog Output Waveform Circuitry
Whether the waveform size is greater than or less than 2,048 points, a waveform can be
generated that is seamless, that is, there will be no gaps or missed points in the output waveform.
If a point is missed for any reason, the waveform circuitry will automatically stop updating the
DAC, and a waveform error signal will be generated that can be monitored in Status Register 1.
An error condition, or underflow, occurs when data is extracted from the DAC FIFO faster than
it enters, such that at one point the DAC FIFO becomes empty.
Underflow errors occur because of software or hardware latencies in acknowledging the signal
requesting more data for the DAC FIFOs. This condition can be prevented in the cyclic mode
where the buffer resides wholly in the DAC FIFO and is cycled through to generate a continuous
waveform. The advantage of having the data in the DAC FIFO is that the FIFO never needs to
have the data refreshed, therefore it is never empty. Rather than requesting new data, the FIFO
simply reuses existing data, removing a large demand on the PC bus bandwidth. Maximum
updating performance is achieved in this mode because it does not rely on the speed of the
computer. All described waveform modes involving cycling within the DAC FIFO can also be
accomplished without the entire buffer fitting inside the FIFO. However, this requires more
software intervention and therefore results in a slower rate and decreased reliability.
FIFO Continuous Cyclic Waveform Generation
In addition to allowing better performance, the cyclic mode provides greater flexibility. Because
the hardware is in full control of the buffer, it can start, stop, and restart the generation of the
waveform as programmed. An example of this added functionality is shown in Figure 3-13.
DACFIFORT*
CYCLICSTOP
Figure 3-13. FIFO Cyclic Waveform Generation with Disable
In this example, the entire buffer fits within the DAC FIFO. After the waveform is initiated, it
cycles and recycles through the buffer. The end of the buffer is indicated by the DACFIFORT*
signal, or DAC FIFO Retransmit. This is a signal generated by the hardware in cyclic mode to
trigger the DAC FIFO to retransmit its buffer. The CYCLICSTOP signal is programmable
through a register in the AT-MIO-64F-5 register set. If this bit is cleared, the DAC FIFO
hardware runs ad infinitum or until the timer update pulse triggering is disabled. If necessary,