Nagasaki PC104-688VL, Руководство пользователя

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NAGASAKI IPC
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PCI VGA Palette Snoop
When Enabled is selected, multiple VGA devices operating on different buses can
handle data from the CPU on each set of palette registers on every video device. Bit
5 of the command register in the PCI device configuration space is the VGA Palette
Snoop bit. (0 is disabled).
Available Options:
Disabled: Data read and written by the CPU is only directed to the PCI VGA devices
palette registers.
Enabled: Data read and written by the CPU is directed to both the PCI VGA devices
palette registers.
Default setting: Disable
Allocate IRQ to PCI AGP
When a PCI or AGP VGA device is installed, you can assign an IRQ to this device.
Selecting Yes, BIOS will auto-assign IRQ to the device. Selecting No, no IRQ will be
assigned to the VGA device.
Available Options: Yes, No
Default setting: No
PCI IDE BusMaster
This option is to specify that the IDE controller on the PCI local bus have bus-mastering
capability.
Available Options: Enable, Disable
Default setting: Disable
DMA Channel 0 – 7
When I/O resources are controlled manually, you can assign each system DMA as one
of the following types, based on the type of device using the interrupt:
ISA/EISA devices comply with the original PC AT bus specification, requiring a specific
interrupt (Such as IRQ5 for COM1).
PnP (PCI/ISA) devices: comply with the Plug and Play standard, whether designed for
PCI or ISA bus architecture.
Available Options: PnP, ISA/EISA
Default setting:
PnP