NAD M56, Руководство по обслуживанию

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3- 53 3- 54
2. BCM7601-2 CIRCUIT DIAGRAM
DDR2_0_DATA[15]
DDR2_0_DATA[8]
DDR2_0_ADDR[5]
DDR2_0_DATA[22]
DDR2_1_DATA[25]
DDR2_1_DATA[24]
DDR2_0_DATA[24]
DDR2_1_ADDR[9]
DDR2_0_ADDR[2]
DDR2_1_DATA[16]
DDR2_1_ADDR[13]
DDR2_0_DATA[13]
DDR2_0_DATA[3]
DDR2_0_DATA[20]
DDR2_0_DATA[4]
DDR2_1_ADDR[10]
DDR2_0_DATA[30]
DDR2_1_DATA[30]
DDR2_1_ADDR[2]
DDR2_0_DATA[12]
DDR2_0_ADDR[11]
DDR2_1_ADDR[6]
DDR2_0_DATA[25]
DDR2_0_ADDR[6]
DDR2_0_DATA[23]
DDR2_1_DATA[14]
DDR2_0_DATA[18]
DDR2_0_DATA[27]
DDR2_0_DATA[31]
DDR2_0_DATA[2]
DDR2_0_DATA[14]
DDR2_0_DATA[21]
DDR2_1_DATA[29]
DDR2_0_ADDR[12]
DDR2_0_ADDR[13]
DDR2_0_DATA[17]
DDR2_0_ADDR[3]
DDR2_1_DATA[12]
DDR2_0_ADDR[4]
DDR2_1_DATA[19]
DDR2_0_ADDR[7]
DDR2_1_DATA[23]
DDR2_1_DATA[0] DDR2_1_DATA[27]
DDR2_0_DATA[19]
DDR2_0_DATA[16]
DDR2_0_DATA[6]
DDR2_0_DATA[10]
DDR2_1_ADDR[12]
DDR2_0_DATA[1]
DDR2_1_DATA[26]
DDR2_0_DATA[28]
DDR2_0_ADDR[10]
DDR2_0_ADDR[8]
DDR2_1_DATA[10]
DDR2_1_DATA[13]
DDR2_1_DATA[1]
DDR2_1_DATA[21]
DDR2_0_DATA[0]
DDR2_0_DATA[26]
DDR2_0_DATA[29]
DDR2_1_DATA[11]
DDR2_0_ADDR[9]
DDR2_0_DATA[7]
DDR2_1_DATA[18]
DDR2_1_ADDR[11]
DDR2_1_DATA[20]
DDR2_1_DATA[2]
DDR2_0_ADDR[0]
DDR2_1_DATA[17]
DDR2_0_DATA[5]
DDR2_0_DATA[11]
DDR2_1_DATA[15]
DDR2_1_DATA[28]
DDR2_0_DATA[9]
DDR2_0_ADDR[1]
DDR2_1_DATA[22]
DDR2_1_DATA[31]
EBI_DATA[5]
EBI_ADDR[24]
EBI_DATA[6]
EBI_DATA[7]
EBI_DATA[3]
EBI_ADDR[25]
EBI_DATA[4]
EBI_DATA[2]
EBI_DATA[1]
EBI_DATA[0]
DDR2_1_ADDR[5]
DDR2_1_ADDR[3]
DDR2_1_ADDR[1]
DDR2_1_ADDR[4]
DDR2_1_DATA[7]
DDR2_1_DATA[3]
DDR2_1_DATA[8]
DDR2_1_DATA[5]
DDR2_1_DATA[9]
DDR2_1_ADDR[0]
DDR2_1_DATA[4]
DDR2_1_ADDR[8]
DDR2_1_DATA[6]
DDR2_1_ADDR[7]
VCC_3V3
VCC_1V2
VCC_1V8
DGND
VCC_1V2
DGND
VCC_3V3
CA2E2
47uF
CA2E3
47uF
DGND
DGND
VCC_1V8
CA2E6
47uF
CA2E5
47uF
CA2E4
47uF
VCC_2V5
DGND
VCC_2V5
CA2E1
47uF
VCC_1V8
DDR2_0_VREF
C278
22uF
R217
1k(1%)
R224
1k(1%)
DGND
C205
0.1uF
C214
0.1uF
C252
0.1uF
C250
0.1uF
C203
0.1uF
C249
0.1uF
C217
0.1uF
C248
0.1uF
C219
0.1uF
C230
0.1uF
C259
0.1uF
C202
0.1uF
C226
0.1uF
C233
0.1uF
C257
0.1uF
C234
0.1uF
C245
0.1uF
C260
0.1uF
C264
0.1uF
C243
0.1uF
C262
0.1uF
C242
0.1uF
C216
0.1uF
C215
0.1uF
C241
0.1uF
C254
0.1uF
C256
0.1uF
C267
0.1uF
C240
0.1uF
C239
0.1uF
C265
0.1uF
C238
0.1uF
C258
0.1uF
C273
0.1uF
C236
0.1uF
C210
0.1uF
C227
0.1uF
C253
0.1uF
C204
0.1uF
C270
0.1uF
C225
0.1uF
C255
0.1uF
C263
0.1uF
C213
1uF
C212
1uF
C246
1uF
C244
1uF
C235
2.2uF
C207
2.2uF
C269
2.2uF
C232
2.2uF
C223
2.2uF
C237
2.2uF
C261
2.2uF
C228
2.2uF
C231
2.2uF
C247
2.2uF
C251
2.2uF
C266
2.2uF
C208
2.2uF
C206
2.2uF
R229
0
C281
0.1uF
DGND
C224
0.1uF
C282
0.1uF
C283
0.1uF
CA2E7
47uF
C284
0.1uF
C285
0.1uF
C286
0.1uF
DDR2_0_DQM2 3:C7
DDR2_1_CLK23_P 3:G6;3:G7 DDR2_0_nCS1 3:C6
VCC_1V8
DDR2_1_DQM2
3:G7
DDR2_0_DQM0 3:C3
DDR2_0_CLK01_P 3:B4;3:C3
DDR2_0_DQS2_N 3:E7
DDR2_1_BA1 3:G3;3:G6
C279
0.1uF
DDR2_1_VREF
DDR2_1_DATA[0-31]
3:K2
C280
22uF
DDR2_1_DQS1_N
3:I4
DDR2_0_DQS0_P 3:E4
DDR2_0_DQM1 3:C3
DDR2_1_CKE 3:G3;3:G6
DDR2_0_VREF
DDR2_0_DQS3_N 3:E7
DDR2_0_BA2 3:C3;3:C6
DDR2_0_DQS2_P 3:E7
DDR2_1_DQS2_P 3:J7
DDR2_1_ADDR[0-13]
3:G2;3:G5
DDR2_0_nCAS
3:C3;3:C6
DDR2_0_BA1 3:C3;3:C6
DDR2_1_DQM0 3:G3
DDR2_1_CLK01_N
3:G3;3:G4
R228
1k(1%)
DDR2_1_DQS1_P 3:I4
DDR2_1_DQS2_N 3:J7
DDR2_1_nRAS 3:G3;3:G6
DDR2_1_DQM3 3:G6
DDR2_0_nRAS
3:C3;3:C6
DDR2_0_CKE
3:C3;3:C6
DDR2_1_DQS0_P 3:I4
DDR2_1_DQS3_N 3:J7
DDR2_0_CLK23_N
3:B7;3:C6
DDR2_0_DQS1_P
3:E4
DDR2_0_nCS0
3:C3
DDR2_1_CLK23_N 3:G6;3:G7
DDR2_0_DATA[0-31]
3:F2
R225 243(1%)
DDR2_1_DQS0_N 3:I4
DDR2_0_DQS3_P
3:E7
DDR2_0_DQS1_N 3:E4
DDR2_0_BA0 3:C3;3:C6
DDR2_1_BA0 3:G3;3:G6
DDR2_1_DQS3_P 3:J7
DDR2_0_ODT
3:E3;3:E6
DDR2_0_CLK23_P 3:B7;3:C6
DDR2_1_nCAS 3:G3;3:G6
DDR2_1_nWE 3:G3;3:G6
R227
1k(1%)
DDR2_0_nWE 3:C3;3:C6
DGND
DDR2_1_CLK01_P 3:G3;3:G4 DGND
DDR2_0_DQM3 3:C6
DDR2_1_BA2
3:G3;3:G6
DDR2_0_CLK01_N 3:B4;3:C3
DDR2_0_ADDR[0-13]
3:B2;3:B5
DDR2_0_DQS0_N 3:E4
DDR2_1_DQM1 3:G3
NAND_ALE
4:B2;5:H6
EBI_nWE0 4:B2;5:H6
EBI_nRW
5:H6
EBI_nCS0 4:A2
DDR2_1_ODT 3:J3;3:J6
EBI_nWE1 5:H6
DGND
NAND_CLE
4:B2;5:H6
EBI_ADDR[24-25]
5:H6
DDR2_1_nCS0 3:G3
EBI_NAND_RB 4:B3
EBI_nCS1 4:A2
EBI_DATA[0-7]
4:B1
CLK33_OUT_PCI_CLK_IN 5:C3
R226 243(1%)
NAND_nRE
4:B2;5:H6
TP201
DDR2_1_nCS1 3:G6
TP202
PCI_nGNT0 5:H6
DGND
IC201
BCM7601 BGA 507Pin (21 x 21) Broadcom
P5
DDR2_0_ADDR_00
K2
DDR2_0_ADDR_01
N7
DDR2_0_ADDR_02
J2
DDR2_0_ADDR_03
L4
DDR2_0_ADDR_04
H1
DDR2_0_ADDR_05
K5
DDR2_0_ADDR_06
J3
DDR2_0_ADDR_07
M5
DDR2_0_ADDR_08
H2
DDR2_0_ADDR_09
K1
DDR2_0_ADDR_10
K4
DDR2_0_ADDR_11
H3
DDR2_0_ADDR_12
J5
DDR2_0_ADDR_13
M2
DDR2_0_BA0
L3
DDR2_0_BA1
M3
DDR2_0_BA2
AB7
DDR2_0_DATA_00
AA4
DDR2_0_DATA_01
AC4
DDR2_0_DATA_02
AB4
DDR2_0_DATA_03
AB5
DDR2_0_DATA_04
AC1
DDR2_0_DATA_05
AA5
DDR2_0_DATA_06
AC5
DDR2_0_DATA_07
AA7
DDR2_0_DATA_08
W3
DDR2_0_DATA_09
Y6
DDR2_0_DATA_10
Y5
DDR2_0_DATA_11
W6
DDR2_0_DATA_12
AA3
DDR2_0_DATA_13
Y3
DDR2_0_DATA_14
AA2
DDR2_0_DATA_15
V2
DDR2_0_DATA_16
V5
DDR2_0_DATA_17
W4
DDR2_0_DATA_18
W5
DDR2_0_DATA_19
U7
DDR2_0_DATA_20
V4
DDR2_0_DATA_21
U5
DDR2_0_DATA_22
V1
DDR2_0_DATA_23
T5
DDR2_0_DATA_24
R5
DDR2_0_DATA_25
T3
DDR2_0_DATA_26
R7
DDR2_0_DATA_27
R6
DDR2_0_DATA_28
U6
DDR2_0_DATA_29
P2
DDR2_0_DATA_30
T6
DDR2_0_DATA_31
AA6
DDR2_0_DM_0
W7
DDR2_0_DM_1
V7
DDR2_0_DM_2
P1
DDR2_0_DM_3
AC2
DDR2_0_DQS_0_P
AC3
DDR2_0_DQS_0_N
Y1
DDR2_0_DQS_1_P
Y2
DDR2_0_DQS_1_N
U4
DDR2_0_DQS_2_P
U3
DDR2_0_DQS_2_N
R4
DDR2_0_DQS_3_P
R3
DDR2_0_DQS_3_N
N4
DDR2_0_nRAS
N6
DDR2_0_nCAS
M1
DDR2_0_nWE
AB1
DDR2_0_CLK01_P
AB2
DDR2_0_nCLK01_N
T1
DDR2_0_CLK23_P
T2
DDR2_0_nCLK23_N
N2
DDR2_0_CKE
P7
DDR2_0_CS0
P4
DDR2_0_CS1
N3
DDR2_0_VREF
J4
DDR2_0_ZQ
N5
DDR2_0_ODT
L5
DDR2_0_TESTOUT
AC10 DDR2_1_ADDR_00
AC6
DDR2_1_ADDR_01
AA10 DDR2_1_ADDR_02
AD6
DDR2_1_ADDR_03
AB9
DDR2_1_ADDR_04
AE6
DDR2_1_ADDR_05
Y10
DDR2_1_ADDR_06
AD5
DDR2_1_ADDR_07
AA9
DDR2_1_ADDR_08
AD4
DDR2_1_ADDR_09
AC7
DDR2_1_ADDR_10
Y9
DDR2_1_ADDR_11
AE4
DDR2_1_ADDR_12
Y8
DDR2_1_ADDR_13
AE8
DDR2_1_BA0
AB8
DDR2_1_BA1
AD8
DDR2_1_BA2
W20
DDR2_1_DATA_00
AA19 DDR2_1_DATA_01
Y19
DDR2_1_DATA_02
AA18 DDR2_1_DATA_03
AA20 DDR2_1_DATA_04
W19
DDR2_1_DATA_05
AE20 DDR2_1_DATA_06
Y18
DDR2_1_DATA_07
AB17 DDR2_1_DATA_08
AE16 DDR2_1_DATA_09
AA17 DDR2_1_DATA_10
AB16 DDR2_1_DATA_11
AC17 DDR2_1_DATA_12
W17
DDR2_1_DATA_13
AD17
DDR2_1_DATA_14
AC18
DDR2_1_DATA_15
AC14
DDR2_1_DATA_16
W15
DDR2_1_DATA_17
AA15
DDR2_1_DATA_18
W16
DDR2_1_DATA_19
AD14
DDR2_1_DATA_20
AD16
DDR2_1_DATA_21
AA14
DDR2_1_DATA_22
AA16
DDR2_1_DATA_23
Y14
DDR2_1_DATA_24
AA12
DDR2_1_DATA_25
AD12
DDR2_1_DATA_26
Y13
DDR2_1_DATA_27
AA13
DDR2_1_DATA_28
Y15
DDR2_1_DATA_29
AC11
DDR2_1_DATA_30
W13
DDR2_1_DATA_31
AB20
DDR2_1_DM_0
Y17
DDR2_1_DM_1
AE14
DDR2_1_DM_2
AB12
DDR2_1_DM_3
AD21
DDR2_1_DQS_0_P
AD20
DDR2_1_DQS_0_N
AE18
DDR2_1_DQS_1_P
AD18
DDR2_1_DQS_1_N
AC15
DDR2_1_DQS_2_P
AB15
DDR2_1_DQS_2_N
AE12
DDR2_1_DQS_3_P
AD13
DDR2_1_DQS_3_N
AC9
DDR2_1_nRAS
Y11
DDR2_1_nCAS
AD9
DDR2_1_nWE
AC19
DDR2_1_CLK01_P
AB19
DDR2_1_nCLK01_N
AC13
DDR2_1_CLK23_P
AB13
DDR2_1_nCLK23_N
AD10
DDR2_1_CKE
W12
DDR2_1_CS0
AA11
DDR2_1_CS1
AE10
DDR2_1_VREF
W10
DDR2_1_ZQ
AB11
DDR2_1_ODT
W8
DDR2_1_TESTOUT
M25
PCI_AD00
M22
PCI_AD01
N21
PCI_AD02
P24
PCI_AD03
L19
PCI_AD04
H25
PCI_AD05
H23
PCI_AD06
J25
PCI_AD07
T23
PCI_AD08
F24
PCI_AD09
R23
PCI_AD10
R22
PCI_AD11
K23
PCI_AD12
F25
PCI_AD13
G23
PCI_AD14
F23
PCI_AD15
G22
PCI_AD16
D25
PCI_AD17
E25
PCI_AD18
L22
PCI_AD19
J23
PCI_AD20
M19
PCI_AD21
J22
PCI_AD22
L20
PCI_AD23
N22
PCI_AD24
P20
PCI_AD25
P21
PCI_AD26
K24
PCI_AD27
N19
PCI_AD28
L21
PCI_AD29
K25
PCI_AD30
R21
PCI_AD31
J21
PCI_CBE00
H24
PCI_CBE01
R20
PCI_CBE02
K21
PCI_CBE03
M20
PCI_PAR
T24
PCI_nFRAME
H22
PCI_nTRDY
P23
PCI_nIRDY
L23
PCI_nSTOP
N20
PCI_nDEVSEL
M23
PCI_CLK_IN
R19
PCI_nPERR
N23
PCI_nSERR
M24
PCI_nRST
T25
PCI_INT_A0
N25
PCI_nREQ0
P25
PCI_nGNT0
H20
EBI_NAND_RB
D23
EBI_ADDR24
E23
EBI_ADDR25
K20
EBI_nCS0
J20
EBI_nCS1
E22
EBI_nCS2
C24
EBI_nCS3
J19
EBI_nRW
C25
EBI_nWE0
F21
EBI_nWE1
G21
EBI_nRD
C23
EBI_nDS
D24
EBI_nTS
IC201
BCM7601 BGA 507Pin (21 x 21) Broadcom
G8
VDD33
G16
VDD33
A17
VDD33
F19
VDD33
K19
VDD33
P19
VDD33
W21
VDD33
F22
VDD33
K22
VDD33
P22
VDD33
B24
VDD33
G12
REG_VDD33
F14
REG_OUT_2P5
AC24
OTP_V2P5
K3
VDD18
P3
VDD18
V3
VDD18
AB3
VDD18
T7
VDD18
Y7
VDD18
AC8
VDD18
W9
VDD18
AC12
VDD18
W14
VDD18
AC16
VDD18
W18
VDD18
AC20
VDD18
F6
VDD12
M10
VDD12
N10
VDD12
P10
VDD12
M11
VDD12
N11
VDD12
P11
VDD12
K12
VDD12
L12
VDD12
R12
VDD12
T12
VDD12
K13
VDD12
L13
VDD12
R13
VDD12
T13
VDD12
K14
VDD12
R14
VDD12
T14
VDD12
M15
VDD12
N15
VDD12
P15
VDD12
M16
VDD12
N16
VDD12
P16
VDD12
J1
VSS
N1
VSS
U1
VSS
AA1
VSS
AD2
VSS
H4
VSS
M4
VSS
T4
VSS
Y4
VSS
AE5
VSS
P6
VSS
V6
VSS
AB6
VSS
AA8
VSS
AE9
VSS
K10
VSS
L10
VSS
R10
VSS
T10
VSS
AB10
VSS
K11
VSS
L11
VSS
R11
VSS
T11
VSS
M12
VSS
N12
VSS
P12
VSS
Y12
VSS
M13
VSS
N13
VSS
P13
VSS
AE13
VSS
M14
VSS
N14
VSS
P14
VSS
D5
NC
D6
NC
E6
NC
E5
NC
E9
NC
F9
NC
F12
NC
E21
NC
F18
NC
G18
NC
G7
NC
G3
NC
H5
NC
H6
NC
J6
NC
K6
NC
L6
NC
M6
NC
L7
NC
M7
NC
U2
NC
W11
NC
AD3
NC
AE3
NC
AC21
NC
AC23
NC
E1
NC
AC25
NC
AD22
NC
AD23
NC
AD24
NC
AE22
NC
AE23
NC
B10
NC
C11
NC
A23
NC
B20
NC
C20
NC
A22
NC
E2
NC
F2
NC
B21
SC_IO_0
C21
SC_CLK_0
D20
SC_RST_0
E20
SC_PRES_0
F20
SC_VCC_0
E17
PKT_CLK0
F17
PKT_DATA0
G17
PKT_SYNC0
B17
PKT_CLK1
C17
PKT_DATA1
D17
PKT_SYNC1
A18
PKT_CLK2
B18
PKT_DATA2
C18
PKT_SYNC2
C19
RMX_CLK0
D19
RMX_DATA0
E19
RMX_SYNC0
E18
RMX_PAUSE0
L14
OBSERV_VDD12
L15
OBSERV_VSS
AB14
VSS
D15 VSS
K15
VSS
R15 VSS
T15
VSS
K16
VSS
L16 VSS
R16
VSS
T16 VSS
Y16
VSS
AE17
VSS
D18
VSS
AB18
VSS
Y20
VSS
A21
VSS
D21
VSS
H21
VSS
M21
VSS
T21
VSS
AE21
VSS
AB22
VSS
E24
VSS
J24
VSS
N24
VSS
U24
VSS
Y24
VSS
VCC_3V3
TP203
TP204
R230 10K
R231 10K
R232 10K
R233 10K
R234 10K
R235 10K
R236 10K
R237 10K
R238 10K
1) a. DQS pairs will eventually have length matching rule to their respective byte lane data
b. CK pairs will eventually have length matching rule to the address lines
2) The decaps and VREF resistors and caps should be laid out near the associated balls. For 7440 they should be
backside in the depopulated ring. VREF is the most sensitive net (in terms of isolation) to route.
3) use top and bottom layers only.
4) Lay out escape plan per attached sketch
5) Complete the layout of the wires in the following order, keeping signals on their layer as much as possible:
CK pairs
DQS diff pairs
DQ and DM
remaining signals
6) Signals can be freely substituted within the following groups: [RS] if this is done, the schematic should be updated to match
DQ[7:0] DQ[15:8] DQ[23:16] DQ[31:24]
7) Diff pairs should be routed together 4 mil etch 4 mil spacing
8) Signals should be routed 4 mil etch 4 mil space min, 8 mil spacing mostly.
9) Keep data lines separate from address lines, to avoid x-talk between the two
10) Prepare wire length report and schedule a review
11) LENGTH RULE: Data bits DDR2_n_DATA[31:0] <= 1.5"
12) Keep decoupling caps on back side out from beneath backing plate.
13) Route clocks as differential pairs - Match differential impedance
60 Ohm to plane,
120 Ohm on pair
DDR2 SDRAM LAYOUT GUIDE
2. BCM7601-2
2009.2.16
place C279 to N3 ball of 7601
place C217 to AE10 ball of 7601