NAD M22, Руководство по обслуживанию, Страница: 8 / 55

Instruction
Decode and
Control
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RA3/AN3/V
REF
+
RA2/AN2/V
REF
-/CV
REF
RA1/AN1
RA0/AN0
RB1/INT1/AN10
Data Latch
Data Memory
Address Latch
Data Address<12>
12
Access BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4 12 4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODL PRODH
8 x 8 Multiply
8
BITOP
8 8
ALU<8>
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
RB2/INT2/AN8
RB3/AN9/CCP2
(1)
PCLATU
PCU
OSC2/CLKOUT
(3)
/RA6
Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR functionality is disabled.
3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information.
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
EUSART Comparator
MSSP
10-bit
ADC
Timer2 Timer1 Timer3 Timer0
CCP2
HLVD
ECCP1
BOR Data
EEPROM
W
Instruction Bus <16>
STKPTR
Bank
8
State machine
control signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1
(3)
OSC2
(3)
V
DD
,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
V
SS
MCLR
(2)
Block
LFINTOSC
Oscillator
16 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSO
OSC1/CLKIN
(3)
/RA7
T1OSI
PORTE
MCLR/V
PP
/RE3
(2)
FVR
FVR
FVR
CV
REF
Address Latch
Program Memory
(8/16/32/64 Kbytes)
Data Latch
PIC18F26K20
MCU BOARD
8