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N.A.T. NAT-FMC-SDR4, Техническое справочное руководство

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NAT-FMC-SDR4 

T

ECHNICAL 

R

EFERENCE 

M

ANUAL 

V1.3 

 

 

 

F

UNCTIONAL 

D

ESCRIPTION

 

- 10 - 

4.

 

F

UNCTIONAL 

D

ESCRIPTION

 

The 

NAT-FMC-SDR4

 can be divided into a number of functional blocks, which are described 

in the following paragraphs.  

As the 

NAT-FMC-SDR4

 is intended to be operated with the 

NAT-AMC-ZYNQUP-FMC

 carrier 

only, the following figure gives an overview on the functional blocks of the whole combination. 

Figure 1 

–

 Block Diagram 

SPI+IO

SPI+IO

14

Tx

Tx

ORx

ORx

Rx

Rx

Tx

Tx

ORx

ORx

Rx

Rx

G

PI

O

RF

-C

TR

L

NAT-FMC-SDR4-T

x2/x4 SerDes*

RF-

Transceiver 

ADRV9009

x2/x4 SerDes*

FM

C 

Co

nn

ec

to

r

V

IT

A

 57

.1

RF-

Transceiver 

ADRV9009

Clock + Sync

HMC7044

JESD204b

Clocking

Clk + 

Sync

Clk + 

Sync

19.2

MHz

Osc

122.88

MHz

VXCO

14

6

FPGA GPIO

GPIO

GPIO

SPI+IO

SPI+IO

14

Tx

Tx

ORx

ORx

Rx

Rx

Tx

Tx

ORx

ORx

Rx

Rx

G

PI

O

RF

-C

TR

L

NAT-FMC-SDR4-M

x2 SerDes

RF-

Transceiver 

ADRV9009

x2 SerDes

FM

C 

Co

nn

ec

to

r

V

IT

A

 57

.1

RF-

Transceiver 

ADRV9009

Clock + Sync

14

6

FPGA GPIO

GPIO

GPIO

Clock + Sync

 

x10 SerDes

JTAG

IPMI

TCLKA-D

MMC

I²C

Si5374 

Clocking

REF_CLK IN
SYS_REF IN

GPU

SD

Card

JESD204B 

CLK/SYNC

SPI

GPIO

User

CLK

USB to 

JTAG and 

UART

TRIG IN/OUT

AMC Ports 0/1 GbE

AMC Ports 2/3, 12-20 Custom

AMC Ports 4-11

PCIe / Ethernet / Custom

FPGA SerDes

FPGA SerDes

FPGA SerDes

FPGA SerDes

FPGA SerDes

FPGA SerDes

FPGA SerDes

FPGA SerDes

FPGA SerDes

FPGA SerDes

FPGA SerDes

CLK OUT

TCLKA-D

1PPS

FPGA Clocks

FPGA

XILINX

Zynq Ult

FFVF1517

ZU7EG

ZU11EG

4x A53 

ARM CPU

(Zynq)

2x

R5

2x

R5

CPU

QSPI

FLASH

4

64

8GB 

DDR4

64

8GB 

DDR4

TRIG IN/OUT

Optional Memory 

Module, 

Memory Type tbd

U

SB

FM

C 

Co

nn

ec

to

r

to

 M

ez

za

n

in

e

JTAG

UART

NAT-AMC-ZYNQUP-SDR only

USB

StratumIII 

12.8MHz RefCLK

CLK 

Switch

 

*Note:

 The number of available SerDes connections per RF-Transceiver varies with the number 

of installed FMCs. Equipped with two FMCs (

NAT-AMC-ZYNQUP-SDR8

 option), each FMC 

owns  four  SerDes  connections, 

two

  for  every  RF-Transceiver.  If  only  one  FMC  is  mounted 

(

NAT-AMC-ZYNQUP-SDR4

 option), a total of eight SerDes connections is available on one 

FMC, which means 

four

 for every RF-Transceiver. 

 

 

Содержание NAT-FMC-SDR4

Страница 1: ...chaft für Netzwerk und Automatisierungs Technologie mbH Konrad Zuse Platz 9 53227 Bonn Germany Phone 49 228 965 864 0 sales nateurope com www nateurope com NAT FMC SDR4 FMC MEZZANINE BOARD DESIGNED BY N A T GMBH TECHNICAL REFERENCE MANUAL V1 3 HW REVISION 1 3 ...

Страница 2: ...and LEDs 12 5 2 Component Connector and Switch Location 13 5 2 1 J1 J2 MULTI COAX CONNECTORS 15 5 2 2 J3 FMC CONNECTOR NAT FMC SDR4 M 16 5 2 3 J3 FMC CONNECTOR NAT FMC SDR4 T 19 5 2 4 J4 GPIO CONNECTOR 22 5 2 5 J5 FMC CONNECTOR NAT FMC SDR4 M ONLY 23 6 SPECIFICATIONS AND COMPLIANCES 26 6 1 Internal Reference Documentation 26 6 2 External Reference Documentation 26 6 3 Standards Compliance 26 6 4 C...

Страница 3: ...NAT FMC SDR4 TECHNICAL REFERENCE MANUAL V1 3 PREFACE 3 6 8 Abbreviation List 28 7 DOCUMENT S HISTORY 29 ...

Страница 4: ...Connector Pin Assignment 22 Table 7 J5 FMC Connector NAT FMC SDR4 M only 23 Table 8 Abbreviation List 28 Table 9 Document s History 29 LIST OF FIGURES Figure 1 Block Diagram 10 Figure 2 Front Panel NAT AMC ZYNQUP SDR8 12 Figure 3 NAT FMC SDR4 T Location Diagram Top 13 Figure 4 NAT FMC SDR4 T Location Diagram Bottom 13 Figure 5 NAT FMC SDR4 M Location Diagram Top 14 Figure 6 NAT FMC SDR4 M Location...

Страница 5: ...ts lost savings delays or interruptions in the flow of business activities including but not limited to special incidental consequential or other similar damages arising out of the use of or inability to use this product or the associated documentation even if N A T or any authorized N A T representative has been advised of the possibility of such damages All registered names trademarks etc are pr...

Страница 6: ...ments to be considered before operating the NAT FMC SDR4 for the first time Functional Description Detailed information on the individual devices and the NAT FMC SDR4 s main features Hardware Description of the connectors switches and LEDs located on the NAT FMC SDR4 Specifications and Compliances Detailed list of specifications abbreviations and datasheets of components referred to in this docume...

Страница 7: ...X TX interfaces one NAT FMC SDR4 T Top mezzanine board needs to be installed For 8 RX TX interfaces one NAT FMC SDR4 M Mid and one NAT FMC SDR4 T Top mezzanines are mandatory Both FMCs are built up similar differences are explained in the relevant sections 2 1 Wireless Applications Due to its powerful FPGA for baseband processing using NAT AMC ZYNQUP FMC as base board and the flexible RF frontend ...

Страница 8: ...board or Mid FMC Backplane Interconnect Via carrier board NAT AMC ZYNQUP FMC Front Panel including NAT AMC ZYNQUP FMC carrier board 4x Tx 4x Rx 4x ORx GPIO RF Control 2x 7 GPIO 1V8 to RF Transceiver 2x 3 GPIO 3V3 to RF Transceiver 6x GPIO 1V8 to FPGA CLK OUT CLK IN JESD204b SYNC for JESD204b PPS IN Trigger IN OUT to FPGA SD card holder UART USB serial console for ARM core and MMC AMC standard LEDs...

Страница 9: ...4 TECHNICAL REFERENCE MANUAL V1 3 QUICK START 9 3 QUICK START For bring up information please refer to the NAT AMC ZYNQUP FMC Technical Reference Manual see chapter 6 1 Internal Reference Documentation for details ...

Страница 10: ...6 FPGA GPIO GPIO GPIO Clock Sync x10 SerDes JTAG IPMI TCLKA D MMC I C Si5374 Clocking REF_CLK IN SYS_REF IN GPU SD Card JESD204B CLK SYNC SPI GPIO User CLK USB to JTAG and UART TRIG IN OUT AMC Ports 0 1 GbE AMC Ports 2 3 12 20 Custom AMC Ports 4 11 PCIe Ethernet Custom FPGA SerDes FPGA SerDes FPGA SerDes FPGA SerDes FPGA SerDes FPGA SerDes FPGA SerDes FPGA SerDes FPGA SerDes FPGA SerDes FPGA SerDe...

Страница 11: ...JESD204B IQ sample data interface to FPGA Supported Tuning range center frequency 75 MHz to 6000 MHz RX gain range 30dB in 0 5dB steps Rx Noise Figure 2dB 800 MHz 3dB 2 4 GHz 3 8 dBm 5 5 GHz Maximum output power 9 dBm 75 MHz f 600 MHz 7 dBm 600 MHz f 4000 MHz 6 dBm 4000 MHz f 4800 MHz 4 5 dBm 4800 MHz f 6000 MHz Tx Error Vector Magnitude EVM 0 5 75 MHz LO 0 7 1900 MHz LO 0 7 3800 MHz LO 1 1 5900 M...

Страница 12: ...ze version the NAT AMC ZYNQUP SDR8 which is fully equipped with two FMCs Figure 2 Front Panel NAT AMC ZYNQUP SDR8 NAT AMC ZYNQUP SDR8 1 HS 1 2 3 G P I O 2 S T Stat Flt D C TX1 ORX1 RX1 TX2 ORX2 RX2 DBG B A TX1 ORX1 RX1 TX2 ORX2 RX2 The LEDs debug interface and SD Card holder are accessible via the NAT AMC ZYNQUP FMC Please check the carrier board s Technical Reference Manual for details refer to 6...

Страница 13: ...5 2 Component Connector and Switch Location Figure 3 NAT FMC SDR4 T Location Diagram Top RF Trans ceiver J3 J4 J2 J1 RF Trans ceiver Power Supply Transformation and De Coupling Figure 4 NAT FMC SDR4 T Location Diagram Bottom Clock and Oscillator Power Supply ...

Страница 14: ...ng Figure 6 NAT FMC SDR4 M Location Diagram Bottom Power Supply J5 Connectors on top side drawings imply the board is orientated with the front panel interfaces to the left side Connectors on bottom side drawings imply the board is orientated with the front panel interfaces to the right side Please refer to the following tables to look up the connector pin assignment of the NAT FMC SDR4 ...

Страница 15: ... routed via the pins and ground connected to the shield Note An associated cable set is available as order option Figure 7 J1 J2 Multi Coax Connectors B A C D E F Table 3 J1 J2 Multi Coax Connectors Pin Assignment Pin Signal Signal Pin J1A TX2_OUT_A TX2_OUT_B J2A J1B ORX2_IN_A ORX2_IN_B J2B J1C RX2_IN_A RX2_IN_B J2C J1D RX1_IN_A RX1_IN_B J2D J1E ORX1_IN_A ORX1_IN_B J2E J1F TX1_OUT_A TX1_OUT_B J2F ...

Страница 16: ...C_P GND GBTCLK0_M2 C_P GND HA00_P_CC GND CLK0_M2C_P GND CLK2_BIDIR_ P 5 GND DP9_M2C_N GND GBTCLK0_M2 C_N GND HA00_N_CC GND CLK0_M2C_N GND CLK2_BIDIR_ N 6 SERDOUT0_A _P GND DP0_M2C_P GND SYNCIN1_A_ P GND LA00_P_CC GND nc GND 7 SERDOUT0_A _N GND DP0_M2C_N GND SYNCIN1_A_ N HA04_P LA00_N_CC LA02_P nc GP_INTERRU PT_A 8 GND DP8_M2C_P GND LA01_P_CC GND HA04_N GND LA02_N GND RX1_ENABLE _A 9 GND DP8_M2C_N ...

Страница 17: ... 19 DP5_M2C_N GND LA14_N GND SYNCOUT0_B _N SPI_CS_B LA16_N LA15_P SYNCOUT1_B _N GPIO_11_1V8 _A 20 GND GBTCLK1_M2 C_P GND LA17_P_CC GND SPI_SCLK_B GND LA15_N GND GPIO_13_1V8 _A 21 GND GBTCLK1_M2 C_N GND LA17_N_CC SYNCIN0_B_P GND LA20_P GND SYNCIN1_B_P GND 22 DP1_C2M_P GND LA18_P_CC GND SYNCIN0_B_ N nc LA20_N LA19_P SYNCIN1_B_ N nc 23 DP1_C2M_N GND LA18_N_CC LA23_P GND nc GND LA19_N GND nc 24 GND DP...

Страница 18: ... SERDIN1_B_ N GND nc FPGA_GPIO_ 1_1V8_A GND LA31_P GND RX1_ENABLE _B GND 34 DP4_C2M_P GND I2C_DEV_A0 nc FPGA_GPIO_ 5_1V8_A SPI_SDIO_B LA31_N LA30_P RX2_ENABLE _B GPIO_12_1V8 _B 35 DP4_C2M_N GND FMC_12POV I2C_DEV_A1 GND SPI_SDO_B GND LA30_N GND GPIO_11_1V8 _B 36 GND SERDIN0_B_P GND FMC_3P3V nc GND LA33_P GND TX1_ENABLE_ B GND 37 GND SERDIN0_B_ N FMC_12POV GND nc HB20_P LA33_N LA32_P TX2_ENABLE_ B G...

Страница 19: ...GND CLK_HMC704 4_SYS_PLL_P 5 GND nc GND JESD_DEVCL K_E_N GND CLK_HMC704 4_FPGA_N GND HMC7044_O UT10_N GND CLK_HMC704 4_SYS_PLL_N 6 SERDOUT2_A _P GND SERDOUT0_A _P GND nc GND GPIO14_1V8_ A GND nc GND 7 SERDOUT2_A _N GND SERDOUT0_A _N GND nc GPIO1_HMC 7044 GPIO15_1V8_ A SYNCOUT0_ A_P nc nc 8 GND nc GND JESD_SYSREF _F_P GND GPIO3_HMC 7044 GND SYNCOUT0_ A_N GND nc 9 GND nc GND JESD_SYSREF _F_N nc GND ...

Страница 20: ... 18 SERDOUT1_B _P GND SPI_CSn GPIO_10_1V8 _A nc GND GPIO_11_1V8 _A GND nc GND 19 SERDOUT1_B _N GND SPI_CLK GND nc nc GPIO_12_1V8 _A LA15_P nc nc 20 GND JESD_DEVCL K_F_P GND JESD_SYSREF _E_P GND nc GND LA15_N GND nc 21 GND JESD_DEVCL K_F_N GND JESD_SYSREF _E_N nc GND GPIO_12_1V8 _B GND nc GND 22 SERDIN1_A_P GND GPIO_14_1V8 _A GND nc nc GPIO_11_1V8 _B FPGA_GPIO_ 2_1V8 nc nc 23 SERDIN1_A_ N GND GPIO_...

Страница 21: ...c 33 GND SERDIN3_B_ N GND nc nc GND SYNCOUT0_B _P GND nc GND 34 SERDIN0_B_P GND I2C_DEV_A0 nc nc nc SYNCOUT0_B _N SYNCIN1_B_P nc nc 35 SERDIN0_B_ N GND FMC_12POV I2C_DEV_A1 GND nc GND SYNCIN1_B_ N GND nc 36 GND SERDIN2_B_P GND FMC_3P3V nc GND SYNCOUT1_B _P GND nc GND 37 GND SERDIN2_B_ N FMC_12POV GND nc FP_JESD_ REFSYNC_IN SYNCOUT1_B _N SYNCIN0_B_P nc nc 38 SERDIN1_B_P GND GND FMC_3P3V GND FP_JESD...

Страница 22: ...0_1V8_B B3 A4 GPIO_1_1V8_A GPIO_1_1V8_B B4 A5 GND GND B5 A6 GPIO_2_1V8_A GPIO_2_1V8_B B6 A7 GPIO_3_1V8_A GPIO_3_1V8_B B7 A8 GND GND B8 A9 GPIO_4_1V8_A GPIO_4_1V8_B B9 A10 GPIO_5_1V8_A GPIO_5_1V8_B B10 A11 GPIO_1_3V3_A GPIO_1_3V3_B B11 A12 GPIO_6_1V8_A GPIO_6_1V8_B B12 A13 GPIO_7_1V8_A GPIO_7_1V8_B B13 A14 GND GND B14 A15 GPIO_2_3V3_A GPIO_2_3V3_B B15 A16 VDDA_1P8_A FMC_3P3V B16 A17 GND GND B17 A18...

Страница 23: ...ND CLK0_M2C_P GND CLK2_BIDIR_ P 5 GND DP9_M2C_N GND GBTCLK0_M2 C_N GND HA00_N_CC GND CLK0_M2C_N GND CLK2_BIDIR_ N 6 100R Term GND DP0_M2C_P GND nc GND LA00_P_CC GND nc GND 7 100R Term GND DP0_M2C_N GND nc HA04_P LA00_N_CC LA02_P nc nc 8 GND DP8_M2C_P GND LA01_P_CC GND HA04_N GND LA02_N GND nc 9 GND DP8_M2C_N GND LA01_N_CC nc GND LA03_P GND nc GND 10 100R Term GND LA06_P GND nc HA08_P LA03_N LA04_P...

Страница 24: ...C GND nc nc LA20_N LA19_P nc nc 23 DP1_C2M_N GND LA18_N_CC LA23_P GND nc GND LA19_N GND nc 24 GND DP9_C2M_P GND LA23_N nc GND LA22_P GND nc GND 25 GND DP9_C2M_N GND GND nc nc LA22_N LA21_P nc nc 26 DP2_C2M_P GND LA27_P LA26_P GND nc GND LA21_N GND nc 27 DP2_C2M_N GND LA27_N LA26_N nc GND LA25_P GND nc GND 28 GND DP8_C2M_P GND GND nc nc LA25_N LA24_P nc nc 29 GND DP8_C2M_N GND nc GND nc GND LA24_N ...

Страница 25: ... C D E F G H J K 37 GND nc FMC_12POV GND nc HB20_P LA33_N LA32_P nc nc 38 DP5_C2M_P GND GND FMC_3P3V GND HB20_N GND LA32_N GND nc 39 DP5_C2M_N GND FMC_3P3V GND FMC_VADJ GND FMC_VADJ GND VIO_B_M2C GND 40 GND nc GND FMC_3P3V GND FMC_VADJ GND FMC_VADJ GND VIO_B_M2C ...

Страница 26: ...pliance AMC 0 R2 0 AMC 1 AMC 2 AMC 3 AMC 4 IMPI V1 5 HPM 1 VITA 57 1 6 4 Compliance to RoHS Directive Directive 2011 65 EU of the European Parliament and of the Council of 8 June 2011 on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS predicts that all electrical and electronic equipment being put on the European market after June 30th 2006 mu...

Страница 27: ...tive is quite restrictive on how such waste of private persons and households has to be handled by the supplier manufacturer however it allows a greater flexibility in business to business relation ships This pays tribute to the fact with industrial use electrical and electronical products are commonly integrated into larger and more complex environments or systems that cannot easily be split up a...

Страница 28: ...vanced Mezzanine Card ARM Processor Architecture with reduced instruction set CPU Central Processing Unit DAC Digital Analog Converter FMC FPGA Mezzanine Card FPGA Field Programmable Gate Array GPIO General Purpose Input Output µC Microcontroller µTCA Micro Telecommunications Computing Architecture MMC Module Management Controller MicroSD Card Micro Secure Digital Memory Card MIMO Multiple Input a...

Страница 29: ...se 26 08 2020 Minor changes Se 1 1 21 10 2020 Added Missing pin assignment of FMC Connector J3 for NAT FMC SDR4 M Adaption to HW Version 1 1 Omission of Connectors J5 J6 Modified pin assignment of FMC Connectors J3 J5 Se 1 2 27 10 2021 Updated Table 6 J4 GPIO Connector Pin Assignment se 13 06 2023 Adaption to HW Version V1 3 se 1 3 15 06 2023 Corrected Table 1 Technical Data regarding number of GP...

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