Multitone RPR750 Series, Руководство пользователя и сервисное руководство, Страница: 28 / 66

TM1215 Iss. 6.0
RPR750
.2.3 Demodulation & Detection (All RF variants)
401 is a multi-functional device, combining the operations of mixer, local oscillator, IF,
he IF amplifier of IC401 amplifies the signal and also removes any AM components in
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he detector circuit is also internal to IC401 and is a Quadrature Demodulator with two
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he output from the detector stage is on Pin 10 of IC401. This gives an audio output to
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he output of the data filter is internally connected in IC401 to the FSK reference voltage
431. The
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dditional facilities provided by IC401 include a 1V constant voltage source, which is fed
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low battery voltage alarm is made available on IC401, Pin 16. This circuit is triggered
.2.4 Decoder Board
he Decoder board is most easily considered in three functional sections: digital
.2.4.1 Digital
his section is based around the 8-bit micro-controller IC1 (MKI variant) or IC12 (MKII
1/IC12 contains a flash-based memory (programmed via SK1 pin 7 PGM, which also
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IC
detector, low battery alarm and a 1V regulator.
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the waveform, in order to shape the data signal to a "square" format, before being passe
to the detector stage.
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inputs. One signal input directly connects internally from the IF amplifier stage and a
second signal from the IF is passed out via Pin 8 to a phase delay circuit, comprising
C445, R426, C444 and ceramic discriminator FL402. The phase delay is dependant o
the frequency of the IF signal and is 90 degrees at the receiver's allocated centre
frequency. The delayed signal is fed back into IC401 on Pin 9.
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Pin 9 of PL401 and test point TP1; the latter providing a measurement test point for
receiver tuning, using SINAD measurement techniques. The detector output also
connects to R414, R411, R410, C421 and C422, which connect back into IC401 o
11 and 12, to form a data filter network in conjunction with the integral op-amp. This is a
unity gain low-pass filter, which reduces high frequency noise.
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(FSKREF) charge/discharge circuit. This circuit is controlled by a logic signal from the
central Processor IC1 on the Decoder PCB, via Pin 14 and determines the
charge/discharge rate of the capacitor used to store the FSKREF voltage, C
reference voltage is fed into the FSK comparator, along with the detected signal from t
low-pass filter. The comparator then "shapes" the FSK data signal, to reduce errors due to
waveform distortion and feeds the resulting signal out on to Pin 15, to be passed on to the
Decoder PCB.
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from the battery via the emitter of TR402. The base of TR402 is controlled by the regulato
circuit via Pin 17 and provides the 1V level onto the collector of TR402. Level monitoring
is fed back into IC401 via Pin 18. This voltage is used to power the RF stages of the
receiver.
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when the battery voltage drops to 1.1V and the output pin becomes "high". This status is
fed to the main processor IC1 on the Decoder board, which then activates the audio and
visual alarm circuits.
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processing, audio amplification and power management.
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variant), a 4kbit serial EEPROM IC2 and the display module (LCM).
IC
allows access to the contents of IC2 via IC1/IC12 and provides all the function control fo
the pager and data decoding. The main clock frequency for the IC is derived from XL3 @
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