5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Title
Size
Document Number
Rev
Date:
Sheet
of
MICRO-START INT'L CO.,LTD.
MS-7377 (BELEM) uBTX
10
PWROK MAP
Custom
32
35
Friday, August 17, 2007
Title
Size
Document Number
Rev
Date:
Sheet
of
MICRO-START INT'L CO.,LTD.
MS-7377 (BELEM) uBTX
10
PWROK MAP
Custom
32
35
Friday, August 17, 2007
Title
Size
Document Number
Rev
Date:
Sheet
of
MICRO-START INT'L CO.,LTD.
MS-7377 (BELEM) uBTX
10
PWROK MAP
Custom
32
35
Friday, August 17, 2007
PWROK MAP
VTT_PWRGOOD signal must be
delayed 1-10ms after
VTT_FSB for proper
clock/cpu function
POWER CONN
PWR_OK
VRM_EN
SLP_S4#/SLP_M#
H_PWRGD
ICH9
VTT_PWG
MS7
Bearlake-Q
PWRGD
Intel LGA775 Processor
VID_GD#
SLP_S3#
PWRBTN
Front Panel
ICH_SYNC#
PS_ON#
MCH_CLPWROK
VRM_GD
3-Phases PWM
Intersil 6312
VRM 11
VRMPWRGD assertion to ICH8 occurs at
least 10ms prior to PWROK_3V assertion
to the ICH9.
CK505
VRM_GD
IT8718F
CK_PWRGD
