Motorola MPC860 PowerQUICC, Руководство пользователя

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MOTOROLA Chapter 23. SCC UART Mode 23-21
Part V. The Communications Processor Module
Table 23-12 describes SCCE Þelds for UART mode.
23.20 SCC UART Status Register (SCCS)
The SCC UART status register (SCCS), shown in Figure 23-12, monitors the real-time
status of RXD. The real-time status of CTS and CD is part of the port C parallel I/O.
Table 23-12. SCCE/SCCM Field Descriptions for UART Mode
Bit Name Description
0Ð2 Ñ Reserved, should be cleared.
3 GLR Glitch on Rx. Set when the SCC encounters an Rx clock glitch.
4 GLT Glitch on transmit. Set when the SCC encounters a Tx clock glitch.
5 Ñ Reserved, should be cleared.
6 AB Autobaud. Set when an autobaud lock is detected. The core should rewrite the baud rate generator with
the precise divider value. See Section 21.4, ÒBaud Rate Generators (BRGs).Ó
7 IDL Idle sequence status changed. Set when the channel detects a change in the serial line. The lineÕs
real-time status can be read in SCCS[ID]. Idle is entered when a character of all ones is received; it is
exited when a zero is received.
8 GRA Graceful stop complete. Set as soon as the transmitter Þnishes any buffer in progress after a
GRACEFUL
STOP TRANSMIT
command is issued. It is set immediately if no buffer is in progress.
9 BRKE Break end. Set when an idle bit is received after a break sequence.
10 BRKS Break start. Set when the Þrst character of a break sequence is received. Multiple BRKS events are not
received if a long break sequence is received.
11 Ñ Reserved, should be cleared.
12 CCR Control character received and rejected. Set when a control character is recognized and stored in the
receive control character register RCCR.
13 BSY Busy. Set when a character is received and discarded due to a lack of buffers. In multidrop mode, the
receiver automatically enters hunt mode; otherwise, reception continues when a buffer is available. The
latest point that an RxBD can be changed to empty and guarantee avoiding the busy condition is the
middle of the stop bit of the Þrst character to be stored in that buffer.
14 TX Tx event. Set when a buffer is sent. If TxBD[CR] = 1, TX is set no sooner than when the last stop bit of
the last character in the buffer begins transmission. If TxBD[CR] = 0, TX is set after the last character is
written to the Tx FIFO. TX also represents a CTS lost error; check TxBD[CT].
15 RX Rx event. Set when a buffer is received, which is no sooner than the middle of the Þrst stop bit of the
character that caused the buffer to close. Also represents a general receiver error (overrun, CD lost,
parity, idle sequence, and framing errors); the RxBD status and control Þelds indicate the speciÞc error.
Bit 0 1 2 3 4 5 6 7
Field Ñ ID
Reset 0000_0000_0000_0000
R/W R
Addr 0xA17 (SCCS1), 0xA37 (SCCS2), 0xA57 (SCCS3), 0xA77 (SCCS4)
Figure 23-12. SCC Status Register for UART Mode (SCCS)