Motorola MPC860 PowerQUICC, Руководство пользователя

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MOTOROLA Chapter 23. SCC UART Mode 23-3
Part V. The Communications Processor Module
¥ Frame error, noise error, break, and idle detection
¥ Transmit preamble and break sequences
¥ Freeze transmission option with low-latency stop
23.2 Normal Asynchronous Mode
In normal asynchronous mode, the receive shift register receives incoming data on RXDx.
Control bits in the UART mode register (PSMR) deÞne the length and format of the UART
character. Bits are received in the following order:
1. Start bit
2. 5Ð8 data bits (lsb Þrst)
3. Address/data bit (optional)
4. Parity bit (optional)
5. Stop bits
The receiver uses a clock 8
´
, 16
´
, or 32
´
faster than the baud rate and samples each bit of
the incoming data three times around its center. The value of the bit is determined by the
majority of those samples; if all do not agree, the noise indication counter (NOSEC) in
parameter RAM is incremented. When a complete character has been clocked in, the
contents of the receive shift register are transferred to the receive FIFO before proceeding
to the receive buffer. The CPM ßags UART events, including reception errors, in SCCE and
the RxBD status and control Þelds.
The SCC can receive fractional stop bits. The next characterÕs start bit can begin any time
after the three middle samples are taken. The UART transmit shift register sends outgoing
data on TXDx. Data is then clocked synchronously with the transmit clock, which may have
either an internal or external source. Characters are sent lsb Þrst. Only the data portion of
the UART frame is stored in the buffers because start and stop bits are generated and
stripped by the SCC. A parity bit can be generated in transmission and checked during
reception; although it is not stored in the buffer, its value can be inferred from the bufferÕs
reporting mechanism. Similarly, the optional address bit is not stored in the transmit or
receive buffer, but is supplied in the BD itself. Parity generation and checking includes the
optional address bit. GSMR_H[RFW] must be set for an 8-bit receive FIFO in the UART
receiver.
23.3 Synchronous Mode
In synchronous mode, the controller uses a 1
´
data clock for timing. The receive shift
register receives incoming data on RXDx synchronous with the clock. The bit length and
format of the serial character are deÞned by the control bits in the PSMR in the same way
as in asynchronous mode. When a complete byte has been clocked in, the contents of the
receive shift register are transferred to the receive FIFO before proceeding to the receive
buffer. The CPM ßags UART events, including reception errors, in SCCE and the RxBD
status and control Þelds. GSMR_H[RFW] must be set for an 8-bit receive FIFO.