22-4
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Part V. The Communications Processor Module
Table 22-1 describes GSMR_H Þelds.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Ñ
IRP
Ñ
GDE
Reset
0
R/W
R/W
Addr
0xA04 (GSMR_H1), 0xA24 (GSMR_H2), 0xA44 (GSMR_H3), 0xA64 (GSMR_H4)
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
TCRC
REVD TRX TTX CDP
CTSP CDS CTSS
TFL
RFW TXSY
SYNL
RTSM RSYN
Reset
0
R/W
R/W
Addr
0xA06 (GSMR_H1), 0xA26 (GSMR_H2), 0xA46 (GSMR_H3), 0xA66 (GSMR_H4)
Figure 22-2. GSMR_HÑGeneral SCC Mode Register (High Order)
Table 22-1. GSMR_H Field Descriptions
Bit
Name
Description
0Ð12
Ñ
Reserved, should be cleared.
13
IRP
Infrared Rx polarity. Determines the polarity of the received signal when SCC2 uses IrDA
encoding/decodingÑfor SCC2 only. See Section 26.18, ÒIrDA Encoder/Decoder (SCC2 Only).Ó
0 Active high polarity. An active high pulse is decoded as 0.
1 Active low polarity. An active low pulse is decoded as 0.
14
Ñ
Reserved, should be cleared.
15
GDE
Glitch detect enable. Determines whether the SCC searches for glitches on the external Rx and Tx
serial clock lines. Regardless of the GDE setting, a Schmitt trigger on the input lines is used to
reduce signal noise.
0 No glitch detection. Clear GDE if the external serial clock exceeds the limits of glitch detection logic
(6.25 MHz assuming a 25-MHz system clock), if an internal BRG supplies the SCC clock, or if
external clocks are used and glitch detection matters less than power consumption.
1 Glitches can be detected and reported as maskable interrupts in the SCC event register (SCCE).
16Ð17 TCRC Transparent CRC (valid for totally transparent channel only). Selects the frame checking provided on
transparent channels of the SCC (either the receiver, transmitter, or both, as deÞned by TTX and
TRX). Although this conÞguration selects a frame check type, the decision to send the frame check is
made in the TxBD. Thus, frame checks are not needed in transparent mode and frame check errors
generated on the receiver can be ignored.
00 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1).
01 CRC16 (BISYNC). (X16 + X15 + X2 + 1).
10 32-bit CCITT CRC (Ethernet and HDLC).
(X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + 1).
11 Reserved.
18
REVD Reverse data (valid for a totally transparent channel only)
0 Normal operation.
1 Reverses the bit order for totally transparent channels on this SCC (either the receiver, transmitter,
or both) and sends the msb of each byte Þrst. Section 27.11, ÒBISYNC Mode Register (PSMR),Ó
describes reversing bit order in a BISYNC protocol.
Содержание MPC860 PowerQUICC
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