Motorola MPC860 PowerQUICC, Руководство пользователя

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MOTOROLA Chapter 8. Instruction and Data Caches 8-27
Part II. PowerPC Microprocessor Module
8.6.4.2 Data Cache Store Miss in Write-Back Mode
In the case of a data cache store miss in write-back mode, the data cache must establish the
block in the cache array before modifying that block. Therefore, a block in the cache array
is selected to receive the data from memory and from the load/store unit. The selection
algorithm gives Þrst priority to invalid blocks. If both blocks in the set are marked invalid,
the block in way 0 is selected. If neither of the two blocks in the selected set are invalid,
then the least recently used block is selected for replacement. If the replacement block is
marked modiÞed-valid, then it is temporarily stored in the copyback buffer to be written to
memory later. Locked cache blocks are never replaced.
After a cache block has been selected, the word-aligned physical address of the store data
is sent to the SIU with a 4-word burst transfer read request. The SIU arbitrates for the bus
and initiates a burst read. The transfer begins with the aligned word containing the
requested data (critical word Þrst), followed by the remaining words of the cache block (if
any), then by any remaining words at the beginning of the block (wrap-around). As the
critical word is received from the internal bus, it is merged in the burst buffer with the store
data from the load/store unit. If no bus errors are encountered during the burst buffer Þll
operation, the cache block is written into the cache array and marked modiÞed-valid. The
data cache does not support further requests until the entire block is written to the cache
array. If the machine has stalled waiting for the store to complete, execution is allowed to
resume when the cache block is written into the cache array.
If a bus error is encountered while loading the target data cache block, even on a word not
accessed by the load/store unit, then the cache block is not modiÞed, and a machine check
exception is generated.
After the cache block with the requested data has been loaded from memory, the cache
block in the copyback buffer is sent to the SIU to be written to memory. The data cache can
support further requests, as long as they hit in the cache, while performing the copyback to
memory. If a bus error is encountered during the copyback, a machine check exception is
generated (the copyback error is an imprecise exception). The address and data in the
copyback buffer can be read as speciÞed in Section 8.3.2.1, ÒReading Data Cache Tags and
Copyback Buffer.Ó
8.6.5 Data Accesses to Caching-Inhibited Memory Regions
For load misses to caching-inhibited memory regions, the data is read from memory but not
placed in the cache and the cache status is not affected.
For store misses to caching-inhibited memory regions, the data is written to memory but
not placed in the cache and the cache status is not affected.
It is considered a programming error if a load, store, or dcbz targeting a caching-inhibited
memory region results in a cache hit. The PowerPC architecture allows the result of such
programming errors to be boundedly undeÞned. Software must ensure that data from a
caching-inhibited regions have not been previously loaded into the data cache, or, if they