Motorola MPC860 PowerQUICC, Руководство пользователя

Страница: 205 / 1106

MOTOROLA Chapter 8. Instruction and Data Caches 8-11
Part II. PowerPC Microprocessor Module
8.3.1.2.3 Instruction Cache Unlock Cache Block Command
The unlock cache block command (IC_CST[CMD] = 0b100) is used to unlock previously
locked cache blocks. To unlock a cache block:
1. Write the address of the cache block to be unlocked to the IC_ADR register.
2. Write the unlock cache block command (IC_CST[CMD] = 0b100) to the IC_CST
register.
If the block is found in the cache (hit), it is unlocked and thereafter operates as a regular
valid cache block. If the block is not found in the cache (miss), no operation is performed.
There are no error cases for the unlock block command.
The instruction cache performs the unlock cache block command in one clock cycle.
8.3.1.2.4 Instruction Cache Unlock All Command
The unlock all command (IC_CST[CMD] = 0b101) is used to unlock the entire instruction
cache with a single command.
When the unlock all command is performed, if a cache block is locked, it is unlocked and
thereafter operates as a regular valid cache block. If a block is not locked or if it is marked
invalid, no operation is performed. There are no error cases for the unlock all command
The instruction cache performs the unlock all command in one clock cycle.
8.3.1.2.5 Instruction Cache Invalidate All Command
The instruction cache invalidate all command (IC_CST[CMD] = 0b110) causes all
unlocked, valid blocks in the instruction cache to be marked invalid. As a result of the
invalidate all command, the LRU bits of all cache blocks point to either the unlocked way
or to way 0 if both ways are unlocked. There are no error cases for the invalidate all
command.
The instruction cache performs the invalidate all command in one clock cycle.
8.3.2 Data Cache Control Registers
The MPC860 implements three special purpose registers (SPRs) to control the data
cacheÑthe data cache control and status register (DC_CST), the data cache address
register (DC_ADR), and the data cache data port register (DC_DAT). The data cache can
be disabled, invalidated, locked, or ßushed by issuing the appropriate commands to the data
cache control registers (DC_CST, DC_ADR, and DC_DAT). Also, the data cache control
registers can be used to read the contents and tags of speciÞc data cache blocks.
DC_CST[DFWT] can be used to force the data cache into write-through mode.
DC_CST[LES] controls true-little endian byte-ordering of the MPC860. See Appendix A,
ÒByte Ordering,Ó for more information.
The mtspr and mfspr instructions are used to access the cache control registers, but they
can be accessed only by supervisor-level programs (that is, when MSR[PR] = 0). Any