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DSP56362 Product Brief

MOTOROLA

DSP56362

24-Bit Audio Digital Signal Processor

Figure 2 DSP56362 Surround Decoder Functionality

Features

Multimode, multichannel decoder software functionality

Dolby Digital and Pro Logic

MPEG2 5.1

DTS

Digital audio post-processing capabilities

Bass management

3D Virtual surround sound

Lucasfilm THX5.1

Soundfield processing

Equalization

Digital Signal Processing Core

100/120 Million Instructions Per Second (MIPS) with an 100/120 MHz clock at a 
nominal 3.3 V

Object code compatible with the DSP56000 core with highly parallel instruction set

Data Arithmetic Logic Unit (Data ALU)

Program Control Unit (PCU)

Direct Memory Access (DMA)

Software programmable PLL-based frequency synthesizer for the core clock

Se

le

c

t

IEC958

Tx

Sr/Sl

I

2

S

Tx

C/Sub

I

2

S

Tx

L/R

I

2

S

Tx

Serial

Host

Interface

General 

Purpose 

I/O

System

Clock

PLL

DSP Clock

JTAG/OnCE™

Interface

SPI/I

2

C

Protocol

User

Programmable

I/O

Dedicated

Debugging

Port

External

Host CPU/

AA0565G

User

Se

le

c

t

Dolby

Digital

MPEG2 

5.1/7.1

DTS

Dolby

Noise

Sequencer

8-bit Data Interface

Left/Right
Stereo Out

Center/
Subwoofer 
Out

Right/Left
Surround
Sound Out

I

2

S

Rx

Input

Buffer

Parallel

Host/Data

Interface

DSP56362

Auto

Detector

Defined
Processing:

Bass mgt

3D Virtual

Surround

Lucasfilm

Soundfields

Equalization

Pro Logic

THX5.1

L/R

I

2

S

Tx

Headphone
Mix Down/
Aux. Sur-

O

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tp

ut D

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la

B

u

ff

er

round

PCM or 

Compresse

d Data

 

   

  

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Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

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Содержание DSP56362

Страница 1: ...e 56300 Motorola Symphony DSP Family The DSP56362 utilizes the single instruction per clock cycle DSP56300 core while retaining code compatibility with the DSP56000 core family The DSP56362 contains audio specific peripherals and an on board software architecture as shown in Figure 2 and is offered in a 100 120 MHz MIPS version at a nominal 3 3 V Figure 1 DSP56362 Block Diagram PLL OnCE Clock Gene...

Страница 2: ...ss DMA Software programmable PLL based frequency synthesizer for the core clock Select IEC958 Tx Sr Sl I2 S Tx C Sub I2 S Tx L R I2 S Tx Serial Host Interface General Purpose I O System Clock PLL DSPClock JTAG OnCE Interface SPI I2 C Protocol User Program m able I O Dedicated Debugging Port External Host CPU AA0565G User Select Dolby Digital M PEG2 5 1 7 1 DTS Dolby Noise Sequencer 8 bit DataInter...

Страница 3: ...Chip Select Logic for glueless interface to SRAMs On chip DRAM Controller for glueless interface to DRAMs Peripheral and Support Circuits Enhanced Serial Audio Interface ESAI includes 6 serial data lines 4 selectable as receive or transmitt and 2 transmitt only Master or slave capability I2 S Sony AC97 and other audio protocol implementations Asynchronous and synchronous operation Serial Host Inte...

Страница 4: ...es that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer How to reach us USA Europe Locations Not Listed Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 303 675 2140 1 800 441 2447 Mfax RMFAX0 email sps mot com TOUCHTONE 602 244 6609 US C...

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