Chapter 13. Physical Layer Interface Controller (PLIC)
13-33
PLIC Registers
13.5.20 D-Channel Request Register (PDRQR)
All bits in this read/write register are cleared on hardware or software reset.
The PDRQR register contains D-channel control bits for all four ports on the MCF5272.
4
DG0
D-channel grant, port 0. See DG1.
3
DC3
D-channel change, port 3.
0 Default reset value.
1 Indicates that a value other than 0xFF (all ones) exists the D-channel receive register.
2
DC2
D-channel change, port 2. See DC3.
1
DC1
D-channel change, port 1. See DC3.
0
DC0
D-channel change, port 0. See DC3.
15
12
11
10
9
8
7
2
1
0
Field
—
SHDD(1) DCNTI(1) SHDD(0) DCNTI(0)
—
DRQ
Reset
0000_0000_0000_0000
R/W
Read/Write
Addr
MBAR + 0x392
Figure 13-32. D-Channel Request Registers (PDRQR)
Table 13-15. PDRQR Field Descriptions
Bits
Name
Description
15–12
—
Reserved, should be cleared.
11, 9
SHDD
D-channel shift direction.
0 D-channel data is msb first. The first bit received is assumed to be the most
significant bit and is loaded into the msb position of the D-channel receive register
for the respective port. SHDD(1) configures the shift direction for ports 1, 2 and 3,
SHDD(0) configures the shift direction for port 0.
1 D-channel data is lsb first for the D channel. The first bit received is assumed to be
the least significant bit and is loaded into the lsb position of the D-channel receive
register for the respective port.
10, 8
DCNTI
D-channel control ignore. Allows the D-Channel contention function to be ignored.
00 contention active on both ports
01 ignore contention on port 0
10 ignore contention on port 1
11 ignore contention on both ports
7–2
—
Reserved, should be cleared.
1–0
DRQ
The value written to these bits is driven onto the DREQ pins associated with port 0
and port 1. When set, a logic high, 1, is driven on to the corresponding pin.
Table 13-14. PDCSR Field Descriptions
Bits
Name
Description
Содержание DigitalDNA ColdFire MCF5272
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