BenQ
Rev 1.0
3.3 Power Supply circuit
VR3
VR2B
VR2
VBATBB
VR1
VR1B
TPL16
1
U1
ULYSSE_uBGA179
B2
C2
C3
B1
C1
D3
D2
D1
F5
E4
E2
E3
E1
F4
F3
F2
F1
G5
G4
G2
G3
G1
H1
H3
H2
H4
H5
J1
J2
J3
J4
K1
K3
K2
K4
J5
L1
L2
L3
M1
N1
M3
M2
N2
P2
N3
P3
L4
M4
N4
P4
K5
L5
N5
P5
M5
K6
M6
P6
N6
L6
K7
L7
P7
N7
M7
M8
N8
P8
L8
K8
L9
N9
P9
M9
K9
M1
0
P1
0
N10
L10
K1
0
P1
1
N11
M1
1
L11
P1
2
N12
P1
3
N13
M13
M12
N14
M14
L12
L13
L14
K11
K13
K12
K14
J11
J12
J13
J14
H10
H11
H13
H12
H14
G14
J10
G12
G13
G11
G10
F14
F13
F12
F11
E14
E12
E13
E11
F10
D14
D13
D12
C14
B14
C12
C13
B13
A1
3
B1
2
A1
2
D11
C11
B1
1
A1
1
E1
0
D10
B1
0
A1
0
C10
E9
C9
A9
B9
D9
E8
D8
A8
B8
C8
C7
B7
A7
D7
E7
D6
B6
A6
C6
E6
C5
A5
B5
D5
E5
A4
B4
C4
D4
A3
B3
A2
P1
A14
P14
GND
BU/PWT
VDDS2
LT/PWL
SDO/INT10n
RX_MODEM
TX_MODEM
SD_IRDA/CLKOUT_DSP
DSR_MODEM/LPG
RTS_MODEM/TOUT
CTS_MODEM/XF
SCLK/INT1n
RX_IRDA
nSCS0/SCL
RXIR_IRDA/X_A1
TX_IRDA
TXIR_IRDA/X_A4
nSCS1/X_A2
nEMU1
nEMU0
nRESPWRON
TCK
TMS
TDO
TDI
nBSCAN
EN_LMM_PWR/X_IOSTRB
IO0/TPU_WAIT
GND
IO1/TPU_IDLE
ADD0
ADD1
VDDS1
ADD2
ADD3
VDD
ADD4
ADD5
ADD6
ADD7
ADD8
ADD9
ADD10
ADD11
A
DD12
A
DD13
G
NDLM
M
A
DD14
IO
2
/IR
Q
4
A
DD15
A
DD16
A
DD17
A
DD18
A
DD19
A
DD20
V
DDLM
M
A
DD21/
CK
16X
_
IRDA
IO
3
/SIM_
R
n
W
nCS
0
GN
D
V
DDS
1
nB
HE
/I
O
14
nCS
1
nCS
2
G
NDLM
M
nCS
3
CS
4/
A
DD22
RnW
VD
D
nF
O
E
/X
_A
3
nB
LE
/I
O
15
nF
WE
/X
_A
0
V
DDS
1
DA
T
A
0
F
D
P/n
IAC
K
DA
T
A
1
GN
D
DA
T
A
2
DA
T
A
3
GN
D
DA
T
A
4
DA
T
A
5
G
NDA
RM
DA
T
A
6
DA
T
A
7
V
DDA
RM
DA
T
A
8
DA
T
A
9
DA
T
A
10
DATA11
DATA12
DATA13
DATA14
GND
DATA15
CLK13M_OUT/START_BIT
nRESET_OUT/IO7
TSPACT11/MCLK
VDDS2
SIM_RST
SIM_CD/MAS0
SIM_PWCTRL/IO5
SIM_IO
SIM_CLK
TSPACT10/nWAIT
VFSRX
VDR
VDX
GNDA1
CLKTCXO
VDDS1
VDDA1
BDX
VCLKRX
BCLKX/IO6
BFSX
BDR
BFSR
BCLKR/ARMCLK
TSPCLKX
GND
EXT_IRQ
TCXOEN
VDD
TSPDO
TSPEN0
TSPEN1
TSPDI/IO4
TSPEN2
TSPEN3/nSCS2
TSPACT0
TSPACT1
VD
D
T
SPAC
T
2
GN
D
T
SPAC
T
3
CLK
3
2K
_O
UT
G
NDA
2
O
S
C32K
_O
UT
OS
C
3
2
K
_
IN
V
DDS
2
T
SPAC
T
4
RF
E
N
/N
O
P
C
GN
D
T
SPAC
T
5
IDDQ
MC
SI_
T
XD
/IO
9
MC
SI_
R
XD
/IO
1
0
M
C
S
I_CLK
/I
O
11
T
SPAC
T
6
/n
C
S
6
MC
SI_
F
SYN
C
H
/IO
1
2
M
CUDI
V
DDLM
M
M
C
UDO
M
CUE
N0
M
CUE
N1/
IO
8
MC
U
E
N
2
/IO
1
3
EXT
_
F
IQ
T
SPAC
T
7
/C
L
KX_
SPI
ON
_
O
FF
IT
_
W
AKEU
P/IN
T
4
n
KBC
0
/N
F
IQ
T
SPAC
T
8
/n
MR
EQ
T
SPAC
T
9
/MAS1
G
NDLM
M
KBC
1
/N
IR
Q
KBC
2
/XD
I_
0
0
KBC
3
/XD
I_
0
1
KBC
4
/XD
I_
0
2
KBR
0
/XD
I_
0
3
KBR
1
/XD
I_
0
4
SD
I/SD
A
KBR
2
/XD
I_
0
5
V
DDLM
M
KBR
3
/XD
I_
0
6
KBR
4
/XD
I_
0
7
GND
VDDS2
VDDS1
C21
10UF
C26
0.1UF
C25 0.1UF
C19
2.2UF
C17 10UF
C20
10UF
R22
0
R15
0
U3
OMEGA
B2
B1
C2
C3
C1
D2
D1
D3
E1
E2
E3
E4
E5
F1
F2
F3
F4
G4
G1
G2
G3
H1
H2
J1
K1
J2
K2
J3
H3
K3
J4
K4
H4
K5
J5
H5
G5
F5
K6
J6
H6
G6
G7
K7
J7
H7
K8
J8
K9
K10
A1
0
B1
0
C9
D8
D9
D10
D7
E7
E8
E9
E1
0
F6
F7
F8
F9
F1
0
G8
G1
0
G9
H10
H8
H9
J1
0
J9
A1
A2
B3
A3
C4
B4
A4
D4
D5
C5
B5
A5
E6
D6
C6
B6
A6
C7
A7
B7
A8
C8
B8
A9
B9
C10
SIO
3
VS1
G
RND2
UP
R
VR
1
B
O
U
T
V
CC2
VR
2
B
O
U
T
VR
2
SEL
VR
2
O
U
T
VR
2
IN
IC
T
L
V
CHG
VBAT
OS
C
A
S
T
EST
R
ESET
Z
RE
F
G
ND
VR
EF
BG
T
R
1
IBIAS
BG
T
R
3
BG
T
R
2
VR
1
O
U
T
BG
T
R
4
FD
B
K
G
RND1
BGTR5
SWITCH
VBACKUP
COMP
VCC1
TDR
TEN
INT2
BDX
BFSX
BDR
BFSR
UEN
UDR
UDX
VCK
VDX
VFS
VDR
AGNDA1
AUXI
MICIP
MICIN
MICBIAS
BUZZOP
RP
W
O
N
PW
O
N
BU
L
IP
BU
L
Q
P
BU
L
Q
M
O
NNO
F
F
R
T
C
_
AL
AR
M
BD
L
IP
BD
L
IM
BD
L
Q
P
BD
L
Q
M
R
ESPW
R
O
N
Z
IN
T
1
AF
C
APC
DA
C
AU
XG
N
D
G
RND3
VC
C
3
VR
3
O
U
T
EAR
N
EAR
P
AU
XO
N
AU
XO
P
VS2
SVDD
SRST3
VAUX
SCLK3
SCLK5
CK13M
SIO5
SRST5
LCDSYNC
ADIN1
ADIN2
ADIN3
ADIN4/TSCXP
ADIN5/TSCYP
TSCXM
TSCYM
TDO
TDI
TCK
TMS
TEST1
TEST2
TEST3
TEST4
BU
L
IM
R54
0
+
-
V
U4A
Back-up Battery
2
1
R16
0
R17
0
C15
2.2UF
Ulysse Core
Memory
Peripherals
Omega Core
BGND
BGND
BGND
BGND
BGND
BGND
BGND
BGND
2.9V@80mA
Omega/Ulysse Analog part
1.8V@120mA
2.9V@120mA
2.9V@50mA
(From Main Battery)
2.0V@50mA
The phone is mainly supplied from the main battery (VBAT) which is
divided into two routes: VBAT is for RF block, vibrator and buzzer;
VBATBB is for baseband block.
The input power (VBATBB) to Nausica is divided into 4 blocks:
VCC1: to provide power for DC/DC and regulator R1 (VR1)
VCC2: to provide power for regulator R1B (VR1B), R2B (VR2B)
and charger pump
VCC3: to provide power for regulator R3 (VR3)
VR2IN: to provide power for regulator R2 (VR2)
NAUSICA provides five low drop-out voltage regulators.
R1
(VR1): 1.8V@50mA; to supply ULYSSE digital core, RTC,
32KHz and the internal SRAM
R2 (VR2): 2.9V@120mA; to supply 13MHz clock, external memory
devices and LCD display
R2B (VR2B): 2.9V@50mA; to supply peripheral devices, I/O to
NAUSICA
R1B (VR1B): 2.0V@50mA; to supply the digital part of NAUSICA
22
R3 (VR3): 2.9V@80mA; to supply analog part of NAUSICA.
Содержание C200
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Страница 4: ...4 May 19 2003 6809464A58 Contents Product Family D10 ...
Страница 18: ...18 May 19 2003 6809464A5 O General Operation Product Family D10 PRELIMINARY ...
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Страница 89: ...BenQ Rev 1 0 48 ...
Страница 90: ...BenQ Rev 1 0 49 ...
Страница 91: ...BenQ Rev 1 0 Radio Frequency function Descriptions Top Side 50 Bottom Side ...
Страница 92: ...BenQ Rev 1 0 51 ...
Страница 95: ...BenQ Rev 1 0 54 Apollo Block Diagram ...
Страница 96: ...BenQ Rev 1 0 Tx Block Diagram 55 ...
Страница 97: ...BenQ Rev 1 0 56 Rx Block Diagram ...
Страница 98: ...BenQ Rev 1 0 57 TX Front End EGSM DCS ...
Страница 99: ...BenQ Rev 1 0 58 Rx Front End EGSM DCS ...
Страница 100: ...BenQ Rev 1 0 59 RF power management ...
Страница 101: ...BenQ Rev 1 0 60 Tx Power ...
Страница 102: ...BenQ Rev 1 0 VCXO 61 ...
Страница 103: ...BenQ Rev 1 0 Base Band full schematic 62 ...
Страница 104: ...BenQ Rev 1 0 RF full schematic 63 ...
Страница 140: ...BenQ Rev 1 0 Replacement Parts Exploded View 99 Fig 1 Mechanical Exploded View I ...
Страница 141: ...BenQ Rev 1 0 Fig 2 Mechanical Exploded View II 100 ...
Страница 142: ...BenQ Rev 1 0 Fig 3 Mechanical Exploded View III 101 ...