Motorola 56F827, Руководство пользователя по оборудованию, Страница: 19 / 56

Program and Data Memory
MOTOROLA Technical Summary 2-3
2.2 Program and Data Memory
The 56F827EVM uses one bank of 128K
×
16-bit Fast Static RAM (GSI GS72116, labelled
U2) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-1
.
This physical memory bank is split into two logical memory banks of 64Kx16-bits: one
for program memory and the other for data memory. By using the hybrid controller’s
program strobe, PS, signal line along with the memory chip’s A0 signal line, half of the
memory chip is selected when program memory accesses are requested and the other half
of the memory chip is selected when data memory access are requested. This memory
bank will operate with zero wait-state accesses while the 56F827 is running at 70MHz.
However, when running at 80MHz, the memory bank operates with four wait-state
accesses. This memory bank can be disabled by removing the jumper at JG3.
Figure 2-1. Schematic Diagram of the External Memory Interface
56F827
GS72116
A0-A15
PS
D0-D15
RD
WR
A1-A16
A0
DQ0-DQ15
OE
WE
CE
1 2
JG3
+3.3V
Jumper Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..