Mitsubishi DPLUS 74SB -BKB, Руководство по обслуживанию

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7-16
Free-running sync signal and self-test pattern
The self-generated free run sync signals are output from HOUT and VOUT pins when ENFREE bit is set.
Four kinds of standard VESA timings are selected by FREE1 and FREE0 bits.
Self-test pattern signal is output form PAT pin when ENPAT bit is set. PAT1 and PAT0 bits select different
self-test pattern.
Fig. 7 Test Pattern
Fig.8 Free-running sync signal and test pattern timing
PAT1 = 0, PAT0 = 0 PAT1 = 0, PAT0 = 1 PAT1 = 1, PAT0 = 0 PAT1 = 1, PAT0 = 1
X00 X01 010 011 110 111
F
H
Hot frequency 31.496kHz 48kHz 63.83kHz 81.25kHz 90.909kHz 106.195kHz
F
V
Ver frequency 59.993Hz 72.072Hz 59.878Hz 64.865Hz 84.8Hz 84.96Hz
T
HT
Hor total time 31.75us 20.833us 15.667us 12.333us 11us 9.417us
T
VT
Ver total time 16.669ms 13.875ms 16.7ms 15.417ms 11.792ms 11.771ms
T
HS
H sync time 3.833us 2.417us 1us 1.083us 1us 0.833us
T
HB
H Back porch +
H Left border
2 us 1.417us 2.417us 1.833us 1.583us 1.417us
T
HF
H Front porch +
H Right border
0.708us 1.125us 0.542us 0.375us 0.375us 0.292us
T
VS
V sync time 2 × T
HT
6 × T
HT
3 × T
HT
3 × T
HT
3 × T
HT
3 × T
HT
T
VB
V Back porch +
V Top border
33 × T
HT
23 × T
HT
38 × T
HT
46 × T
HT
44 × T
HT
46 × T
HT
T
VF
V Front porch +
V Bottom border
11 × T
HT
38 × T
HT
3 × T
HT
2 × T
HT
2 × T
HT
2 × T
HT
T
VIDEO
Video pulse width 41.67ns 41.67ns 41.67ns 41.67ns 41.67ns 41.67ns