Mitsubishi Electric MELSEC iQ-R Series, Руководство по программированию

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11 PROCESS CONTROL INSTRUCTIONS
11.3 Control Operation Instructions
1253
11
■
Variation rate & upper/lower limiter (7)
The variation rate and upper/lower limits of the input value (E1) are checked, and the data after the processing and an alarm
are output.
Variation rate limiter processing performs the following operations, and outputs the result to the output variation rate alarm
(BB5) of (d1) and the DMLA of the alarm detection (ALM).
*1 If the DMLI or ERRI of the disable alarm detection (INH) is set to 1, the output variation rate alarm (BB5) and the DMLA of the alarm
detection (ALM) are set to 0.
Upper/lower limiter processing performs the following operations, and outputs the result to the output upper limit alarm (BB3);
output lower limit alarm (BB4); MHA and MLA of the alarm detection (ALM); and MHA2 and MLA2 of the alarm detection
(ALM2).
*2 If the MHI or ERRI of the disable alarm detection (INH) is set to 1, the output upper limit alarm (BB3) and the MHA of the alarm detection
(ALM) are set to 0.
Note that the MHA2 of the alarm detection 2 (ALM2) remains 1.
*3 If the MLI or ERRI of the disable alarm detection (INH) is set to 1, the output lower limit alarm (BB4) and the MLA of the alarm detection
(ALM) are set to 0.
Note that the MLA2 of the alarm detection 2 (ALM2) remains 1.
*4 If the specified control cycle is not reached, the MHA2 and MLA2 status of the alarm detection 2 (ALM2) are held.
■ Output conversion processing (8)
The output value (BW) is calculated from the following expression.
■
Loop stop processing (9)
The following processing is performed according to the SPA status of the alarm detection (ALM).
■
Control cycle determination (10)
If the specified control cycle is not reached, "mode determination processing (6)" is performed regarding T as MV.
If the specified control cycle is reached, "SV setting processing (1)" is performed.
Operation error
Condition BB5, DMLA T1
|T-MV|

DML 0 T
(T - MV) > DML 1
*1
MV + DML
(T - MV) < -DML 1
*1
MV - DML
Condition BB4, MLA, MLA2
*4
BB3, MHA, MHA2
*4
MV
T1 > MH 0 1
*2
MH
T1 < ML 1
*3
0 ML
ML

T1

MH 0 0 T1
SPA status Processing details
1 The loop stops. The following operations are performed and the instruction ends.
• The last output value (BW) is held.
• The DVLA, MHA, MLA, and DMLA of the alarm detection (ALM) are set to 0.
• The MHA2 and MLA2 of the alarm detection 2 (ALM2) are set to 0.
• The control mode (MODE) is set to MAN.
• All of the alarm bits (BB1, BB2, BB3, BB4, and BB5) are set to 0.
0 The loop runs and "control cycle determination processing (10)" is performed.
Error code
(SD0) Description
3400H An invalid operation (such as division by zero) is performed.
3402H The value specified by (s1), (s2), or (d2) is a subnormal number or NaN (not a number).
3403H An overflow has occurred.
3405H The control cycle (CT) setting is less than 0.
The execution cycle (

T) setting is less than 0.
The value divided the control cycle (CT) by the execution cycle (

T) exceeds 32767.
BW= ×MV+NMIN
100
NMAX-NMIN