8 MULTIPLE CPU SYSTEM FUNCTIONS
8.4 Data Communication Between CPU Modules
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8
Communication using fixed cycle communication area
Data communication using the fixed cycle communication area is performed by using a multiple CPU synchronous interrupt
program (I45).
Multiple CPU synchronous interrupt
Execute a multiple CPU synchronous interrupt program (I45) at the timing of the cycle of the fixed cycle communication set to
the parameter. By using the multiple CPU synchronous interrupt function, data can be communicated between CPU modules
synchronously with the cycle of the fixed cycle communication. (The data communication timing between CPU modules is
synchronized.)
*1 Performed with the C Controller module dedicated functions (CCPU_ToBufHG_ISR, CCPU_FromBufHG_ISR).
Data communication will not be performed if the multiple CPU synchronous interrupt program (I45) is not
registered.
No.
Processing
Description
Receiving data from another CPU
(refresh)
The data received from another CPU module is read to a device. (The data in the host CPU receive area
is read.)
Operation processing
Multiple CPU synchronous interrupt program is executed.
Sending data to another CPU (refresh)
The data to be sent to another CPU module is written from a device. (The data is written to the host CPU
send area.)
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Cycle of fixed cycle communication
Cycle of fixed cycle communication
Multiple CPU synchronous
interrupt program execution time
CPU module (CPU No.1)
Normal program
Pause
Pause
Multiple CPU synchronous interrupt program
Multiple CPU synchronous interrupt program
Multiple CPU
synchronous
interrupt program
Refresh
Operation
processing
Refresh
Refresh
Operation
processing
Refresh
Fixed cycle communication
area
Send area of
CPU No.1
Read
Write
Send data of
CPU No.2
Send data of CPU No.2
Receive area of
CPU No.1
Send data of
CPU No.1
Receive area of
CPU No.2
Read
Write
Send area of
CPU No.2
Fixed cycle communication
area
Refresh
Operation
processing
Refresh
Refresh
Operation
processing
Refresh
Multiple CPU
synchronous
interrupt program
Multiple CPU synchronous interrupt program
Multiple CPU synchronous interrupt program
Normal program
Pause
Pause
CPU module (CPU No.2)
Multiple CPU synchronous
interrupt program execution time
Содержание MELSEC iQ-R C R12CCPU-V
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