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MT90840

Preliminary Information

2-236

Functional Description

The MT90840 Distributed Hyperchannel Switch is a
large switching, multiplexing, and rate-adapting
device. The MT90840 bridges serial-bus telecom
components, using the Mitel ST-BUS or other
industry-standard serial buses, onto a higher speed
“backbone”. Mixed data, voice and video signals can
be time-interchanged or multiplexed from serial Time
Division Multiplexed (TDM) streams onto a high
speed parallel bus. The parallel bus can be used for
interconnect, or an external framer can be connected
to the parallel bus to access serial isochronous
backbones operating at up to 155 Mbps SONET
rates (STS-3).

The MT90840 Distributed Hyperchannel Switch
supports real-time multimedia applications through
constant delay switching. Multimedia data at N x 64
kbps rates uses N bytes (“time slots”, or “channels”)
per 125

µ

sec frame. This is also referred to as

hyperchannel data. To ensure the integrity of data at
N x 64 kbps rates, the network must ensure that the
N bytes in a given input frame remain together as a
frame, and arrive at the destination as a frame. The
MT90840 supports this requirement by providing
constant delay (frame integrity) which ensures that
the multiple time slots of associated data remain in
the intended order.

Total TDM channel capacity of the MT90840 at
maximum data rates is:
• 512 serial input time slots,
• 512 serial output time slots,
• 2430 parallel input time slots, and
• 2430 parallel output time slots.
The number of time slots available is dependent
upon the selected data rates, and is reduced at lower
data rates.

Figure 1 shows the MT90840 functional block
diagram. The figure shows the TDM data paths and
the device interfaces.

The MT90840 has three main TDM data paths:
• Transmit Path: serial port input (STi) to parallel port
output (PDo),
• Receive Path: parallel port input (PDi) to serial port
output (STo),
• Bypass and Parallel-Switching: PDi to PDo.

In addition, Mitel Message Mode capabilities allow
the user to force data on TDM output time slots and
to monitor TDM input time slots through the
microprocessor port.

The MT90840 has four main interfaces:
• the serial TDM bus interface (STi, STo and timing),
• the parallel TDM bus interface (PDi, PDo and
timing) with programmable control outputs (CTo),
• the microprocessor (CPU) interface,
• the test interface (JTAG).

The MT90840 supports four major timing/switching
modes:
• TM1/Ring Master: PDo timing slaved to STi/o
timing, PDi timing elastic;
• TM2/Ring Slave: PDo and STi/o timing slaved to
PDi;
• TM3/Bus Slave: PDo and PDi timing tied together,
STi/o timing slaved to parallel bus;
• TM4/Parallel Switching: parallel channel switching
from PDi to PDo.

Other features of the MT90840 are programmable for
individual TDM channels on the serial and parallel
ports (per-channel features):
• Mitel Message Mode,
• Per-channel output enable,
• Per-channel bypass (parallel bus),
• Programmable CTo control outputs (parallel bus),
• Per-channel direction control (serial bus).

Device Operation

Time Slot Interchange Operation (Switching)

The MT90840 provides access and time slot
interchange (switching) functions between the serial
and parallel TDM data ports. Switching is provided
on three paths: transmit (serial input to parallel
output), receive (parallel input to serial output) and
bypass/parallel-switching (parallel input to parallel
output). Switching functions between serial data
streams are not provided.

The MT90840 guarantees wideband or
hyper-channel data integrity through the switch by
using constant delay switching. This is done by
storing a full frame (125

µ

sec) of data at the input

rate and then, under control of the Connection
Memory for that path, reading the frame at the output
data rate (frame integrity). Therefore the Transmit
Path and the Receive Path each have separate Data
and Connection Memories.

Switching in a given data path is controlled by
programming the Connection Memory for that path.
Each output time slot has a control-address in the
path’s Connection Memory. Each input time slot has

Содержание MT90840

Страница 1: ...ther devices Diagnostic alarm functions and clock phase status word for clock monitoring IEEE 1149 JTAG boundary scan port Applications Bridging ST BUS MVIP buses to high speed Time Division Multiplex...

Страница 2: ...TDI VSS PPFRi VDD AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 R W DS RD VDD AS ALE CS DTA RES IC VSS VSS VDD NC STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 C4 8R1 C4 8R2 NC F0i o VSS VDD NC CTo3 CTo2 CTo1 CTo0 VSS VD...

Страница 3: ...be applied during power up to bring the MT90840 internal circuitry to a defined state Serial and parallel TDM outputs STo0 7 STi0 7 and PDo0 7 are held in high impedance state after reset until progra...

Страница 4: ...l port data bytes in the transmit direction and operate at data rates up to 19 44 Mbyte s 42 89 PPFTi o Parallel Port Framing Transmit Bidirectional This signal delineates the start of a new data fram...

Страница 5: ...ance For applications with the serial port running at 8 192 Mbps this output is not used and an 8 192 MHz clock source must be supplied at C4 8R1 or C4 8R2 66 73 17 24 STo7 STo0 Serial Output Streams...

Страница 6: ...allel Switching PDi to PDo In addition Mitel Message Mode capabilities allow the user to force data on TDM output time slots and to monitor TDM input time slots through the microprocessor port The MT9...

Страница 7: ...Ch 63 Bit 1 Ch 63 Bit 0 Ch 0 Bit 7 Ch 0 Bit 6 Ch 0 Bit 5 ch 127 Serial I O 8 Mbps 8 MHz C4 8R1 2 4 MHz b3 ch 127 b2 ch 127 b1 ch 127 b0 ch 0 b7 ch 0 b6 ch 0 b5 ch 0 b4 Frame Boundary Established by P...

Страница 8: ...Path Data Memory to the serial outputs This path is controlled by the contents of the Rx Path Connection Memory The Rx Path Connection Memory is programmed for each output time slot with the address...

Страница 9: ...mode is balanced in that there are always 8 inputs and 8 outputs during a time slot If a specific time slot in an output stream e g STo0 channel7 is programmed in the Rx Path Connection Memory as an i...

Страница 10: ...isrupted Parallel Data Port The MT90840 parallel port is composed of an 8 bit wide Parallel Data Output Port PDo0 7 a 4 bit wide Control output port CTo0 3 an 8 bit wide Parallel Data Input Port PDi0...

Страница 11: ...g from PDi to PDo The TM1 0 bits in the TIM Register are used to select the timing modes The PFDI and SFDI bits in the same register can be used to enable parallel device sub modes of TM1 and TM2 resp...

Страница 12: ...t available for operation at 6 48 Mbyte s Timing Mode 2 TM2 Ring Slave Asynchronous Parallel Port With ST BUS Clock Slave Timing Mode 2 is used where the main TDM clock reference resides on the parall...

Страница 13: ...XPAA interrupt source At 8 192 MHz the generated clock is input to the MT90840 at C4 8R1 or C4 8R2 and is also supplied directly to the serial bus the SPCKo output is not used at 8 192 MHz The serial...

Страница 14: ...e synchronized and both aligned with PPFRi A fixed offset exists between F0o and PPFRi due to serial to parallel conversion The MT90840 will align F0o so that it proceeds PPFRi by 3 8 sec In TM3 the i...

Страница 15: ...put Enable and Message Mode On the serial port the per channel features are Output Enable Message Mode and Direction Control These functions are generally available in all of the data rates and timing...

Страница 16: ...Dmin 7 7 sec Note 1 D Dmin 1 frame Po Si 132 7 sec Po Si Min 7 7 sec Avg 133 sec Max 258 sec TM1P S All Dmin ELDmin 4 4 sec Note 2 D 1 frame ELD So Pi 125 sec ELD So Pi Min 4 4 sec Max 379 sec TM2 P S...

Страница 17: ...l is controlled by the DC bit in the appropriate byte of the Receive Path Connection Memory High RPCM High When DC is HIGH the matching channel is an output The per channel direction control feature o...

Страница 18: ...address in the RPCM CPU accesses require the LSB of the CAR Register and the 7 LSBs of the address bus When the DC bit for a specific output channel is LOW that channel is output on the STi pin rather...

Страница 19: ...ss in the TPDM CPU reads require the 2 LSBs of the CAR Register and the 7 LSBs of the address bus The source channel address value written in the TPCM requires 9 bits Figure 14b shows how the Receive...

Страница 20: ...any internal memory access is performed In the MT90840 the AD7 address pin must be kept LOW when addressing the internal registers as depicted in Table 2 When input address pin AD7 is HIGH input addr...

Страница 21: ...pins hold valid read data Numerous reads within the same memory page can be performed without having to re write the Control Register CPU reads of the Data and Connection memories must be multiplexed...

Страница 22: ...d verify address 0 after a block of TPCM writes If address 0 is corrupted one of the writes occurred during a clock correction Clock Quality and TM2 RPCM Access Integrity In Timing Mode 2 the serial f...

Страница 23: ...s asserted during block programming a framing error has occurred and the block programming should be repeated Timing Mode Initialization On system power up the CPU should program the MT90840 IMS GPM a...

Страница 24: ...y scan operation and normal chip operation Boundary Scan Instruction Register In accordance with the IEEE 1149 1 standard the MT90840 uses public instructions listed in Table 3 Instruction Register Th...

Страница 25: ...l zeros into the scan path register will set all outputs to tristate outputs disabled Please visit our web site at www semicon mitel com to download a BSDL file for the MT90840 Cells Definition Note 1...

Страница 26: ...MHz serial port reference clock to be taken from input pin C4 8R1 If LOW the reference is taken from input pin C4 8R2 default TCP Parallel Port Transmit Clock Polarity To allow the MT90840 parallel p...

Страница 27: ...MSKn is set HIGH the corresponding interrupt source is enabled and the IRQ pin will respond to that interrupt source if set LOW the corresponding interrupt source is masked When masked an interrupt so...

Страница 28: ...input address lines or TPCM address bits used to select the time slot 2 Mbps Balanced 8i x 8o 256 channels HA7 AD6 AD5 AB7 AB5 AD4 AD0 AB4 AB0 32 time slots 2 Mbps Add Drop 16 i o 512 channels HA8 HA...

Страница 29: ...nnel In all timing modes except TM4 only bit AB8 is used along with bits AB0 7 in TPCM Low to select one of 512 serial source channels from the serial port side to be transmitted on this output channe...

Страница 30: ...ts or inputs or any mixed combination If DC is LOW this serial port channel is defined as input If DC is HIGH this channel is defined as output Note that the CPU still has to set OE to enable the outp...

Страница 31: ...and give the user access to the payload of the high speed frame The MT90840 provides an 8 bit bidirectional parallel data port which directly interfaces to a high speed framer parallel data interface...

Страница 32: ...Current at Digital Outputs IO 40 mA 4 Storage Temperature TS 65 150 C 5 Package Power Dissipation PD 2 W Recommended Operating Conditions Voltages are with respect to ground VSS unless otherwise stat...

Страница 33: ...19 44 MHz 60 40 duty cycle clock at PCKR C4 8R1 input with min 115 ns semi cycle 3 C4 8 Input Clock Width LOW 4 096 MHz 2 048 4 096 Mbps 8 192 MHz 8 192 Mbps SPCKo Output Clock Width LOW from internal...

Страница 34: ...bps STi Input Setup Time from C4 8 input edge in TM1 2 048 and 4 096 Mbps STi Input Setup Time from C4 8 input edge at 8 192 Mbps STi o0 3 tstis 28 41 0 0 ns ns ns SPCKo CL 30pF SPCKo CL 150pF TM1 and...

Страница 35: ...ch 31 tstih tstis tclkh Serial Port with Negative Polarity F0 ST BUS tsod tfrh tfrs tclk tclkl tT STo0 7 C4 8R1 4 096 MHz STi0 7 tstis tstih F0i input tfrs tfrh tfrw bit 7 ch 0 bit 6 ch 0 bit 7 ch 0...

Страница 36: ...stis tstih F0o output bit 7 ch 0 bit 6 ch 0 bit 7 ch 0 bit 0 ch 31 bit 0 ch 31 Serial Port with Positive Polarity F0 GCI tdf 8 kHz tdf tt tclkh tclkl tclk SPCKo tT STi0 7 STo0 7 4 096 MHz bit 7 ch 0 b...

Страница 37: ...ch 0 bit 7 ch 0 STo0 7 C4 8R1 4 096 MHz STi0 7 F0i input bit 7 ch 0 8 kHz 8 kHz Serial Port with Negative Polarity F0 ST BUS Serial Port with Positive Polarity F0 GCI tt tclkh tclk tclkl tstis tstih...

Страница 38: ...i0 7 F0o output bit 7 ch 0 bit 6 ch 0 bit 7 ch 0 STo0 7 SPCKo 4 096 MHz STi0 7 F0o output bit7 ch 0 8 kHz 8 kHz F0 Frame Sync with Negative Polarity SPFP 0 F0 Frame Sync with Positive Polarity SPFP 1...

Страница 39: ...ates STo0 7 C4 8R1 8 192 MHz STi0 7 F0i input bit 0 ch 127 bit 7 ch 0 bit 6 ch 0 bit 7 8 kHz Note Polarity of F0i is automatically detected in TM1 tstis tstih tfrs tfrh tfrw tsod tt tclkh tclk tclkl E...

Страница 40: ...P 1 tstis tstih tdf tdf tsod tt tclkh tclk tclkl STo0 7 C4 8R1 8 192 MHz STi0 7 F0o output bit 7 ch 0 bit 6 ch 0 bit 7 8 kHz Frame Sync with Negative Polarity SPFP 0 tstis tstih tdf tdf tsod tt tclkh...

Страница 41: ...m 1 byte m byte m 1 CTo corresponding to byte m CTo corresponding to byte m 1 PCKT PCKR tcdf TCP 0 tcdf CTo corresponding to byte m CTo corresponding to byte m 1 byte 0 tsod PDo0 7 byte 1 tPPFH PCKT P...

Страница 42: ...50pF 6 CTo0 3 output delay from PCKR PCKT transmit edge tcdf 26 28 ns CL 30pF CL 50pF 7 PDo delay from Active to High Z tza 26 ns CL 30pF RL 1K 8 PDo delay from High Z to Active taz 28 ns CL 30pF RL...

Страница 43: ...FP HIGH If PPFP is LOW the PPFT line will have negative pulse polarity tdf tdf PCKT C4 8R1 or C4 8R2 PPFTo tpv ST BUS Mode tpv PDo7 0 0 n n 1 1 2 n 2 Note The MT90840 will correct phase relation in TM...

Страница 44: ...after RD WR tcsrw 0 ns 7 CS setup from RD tcsr 0 ns 8 Data hold after RD tdhr 10 15 22 30 ns ns CL 30 pF CL 150 pF 9 WR delay after ALE falling talwr 15 ns 10 CS setup from WR tcsw 0 ns 11 Data setup...

Страница 45: ...275 Figure 32 Intel National Multiplexed Bus Timing ALE AD0 AD7 CS RD WR DTA talw tads tadh DATA ADDRESS talrd tcsrw tdhr tdhw tcsw talwr takd tddr takh 2 0V 0 8V 2 0V 0 8V 2 0V 0 8V 2 0V 0 8V 2 0V 0...

Страница 46: ...ng tcsh 0 ns 6 CS setup from DS rising tcss 0 ns 7 Data setup on write tdsw 10 8 Data hold after write tdhw 0 ns 9 DS Inactive to AS Falling Edge tdss 23 ns 10 R W setup from DS rising trws 5 ns 11 R...

Страница 47: ...ure 33 Motorola Multiplexed Bus Timing CS DTA AD0 13 RD DS R W AS ADDRESS ADDRESS DATA DATA trwh trws tasw tdsh tads tadh tdhw tdhr tcss tcsh takd takh tddr 2 0V 0 8V 2 0V 0 8V 2 0V 0 8V 2 0V 0 8V 2 0...

Страница 48: ...0 ns 2 TCK period width LOW ttclkl 40 ns 3 TCK period width HIGH ttclkh 40 ns 4 TDI setup time to TCK rising tdisu 2 ns 5 TDI hold time after TCK rising tdih 33 ns 6 TMS setup time to TCK rising tmssu...

Страница 49: ...erning dimensions are in millimeters 3 Dimensions in inches are not exact 4 For D E add for allowable Mold Protrusion 0 010 50 1 80 30 81 100 31 51 Pin 1 indicator E b e L L1 Notes 1 Not to scale 2 Go...

Страница 50: ...MT90840 Preliminary Information 2 280 Notes...

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