MIPS MIPS32 74K Series, Руководство по программированию

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Kernel-mode (OS) programming and Release 2 of the MIPS32® Architecture
69 Programming the MIPS32® 74K™ Core Family, Revision 02.14
Both these modes need to be explicitly enabled by setting bits in the Config3 register; if you don’t do that, the
CPU behaves just as the original (release 1) MIPS32 specification required.
• Shadow registers - alternate sets of registers, often reserved for interrupt handlers, are described in Section 5.4,
"Shadow registers" . Interrupt handlers using shadow registers avoid the overhead of saving and restoring user
GPR values.
• The Cause[TI] , Cause[FDCI] ,and Cause[PCI] bits (see Section B.1.3.1 “The Cause register” ) provide a direct
indication of pending interrupts from the on-core timer, fast debug channel, and performance counter subsystems
(these interrupts are potentially shared with other interrupt inputs, and it previously required system-specific pro-
gramming to discover the source of the interrupt and handle it appropriately).
The new interrupt options are enabled by the IntCtl register, whose fields are shown in Figure 5.1 .
Figure 5.1 Fields in the IntCtl Register
IntCtl[IPTI,IPPCI,IPFDCI] : IPTI , IPPCI , and IPFDCI are read-only 3-bit fields, telling you how internal timer, perfor-
mance counter, and fast debug channel interrupts are wired up. They are relevant in non-vectored and simple-vec-
tored ("VI") interrupt modes, but not if you’re using an EIC interrupt controller.
Read this field to get the number of the Cause[IPnn] where the corresponding interrupt is seen. Because
Cause[IP1-0] are software interrupt bits, unconnected to any input, legal values for IntCtl[IPTI], IntCtl[IPPCI] , and
IntCtl[IPFDCI] are between 2 and 7.
The timer, performance counter, and fast debug channel interrupt signals are taken out to the core interface and the
SoC designer connects them back to one of the core’s interrupt inputs. The SoC designer is supposed to hard-wire
some core inputs which show up as the
IntCtl[IPTI,IPPCI,IPFDCI] fields to match.
IntCtl[VS] : is writable to give you software control of the vector spacing; if the value in VS is VS, you will get a spac-
ing of 32
×
2
(VS-1)
bytes.
Only values of 1, 2, 4, 8 and 16 work (to give spacings of 32, 64, 128, 256, and 512 bytes respectively). A value of
zero gives a zero spacing, so all interrupts arrive at the same address — the legacy behavior.
5.2.1 Traditional MIPS
®
interrupt signalling and priority
Before we discuss the new features, we should remind you what was there already. On traditional MIPS systems the
CPU takes an interrupt exception on any cycle where one of the eight possible interrupt sources visible in
Cause[IP]
is active, enabled by the corresponding enable bit in Status[IM] , and not otherwise inhibited. When that happens con-
trol is passed to the general exception handler (see Table 5.1 for exception entry point addresses), and is recognized
by the “interrupt” value in Cause[ExcCode] . All interrupt are equal in the hardware, and the hardware does nothing
special if two or more interrupts are active and enabled simultaneously. All priority decisions are down to the soft-
ware.
Six of the interrupt sources are hardware signals brought into the CPU, while the other two are “software interrupts”
taking whatever value is written to them in the
Cause register.
31 29 28 26 25 10 9 5 4 0
IPTI IPPCI IPFDCI 0 VS 0
X X X 0 0