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miriac MPX-S32G274A User Manual
V2.1
24/76
© MicroSys Electronics GmbH 2020
The f ollowing table shows the available clocks conf igured as primary interf ace on
the MPX-S32G274A:
S32G274A
Module Connector
Ball
Signal
Pin
Signal
I/O Range
Signal
conditioning
Frequency
E19
SD0_CLK
→
T2
SD_CLK
+VREF3
SR: 22R
t.b.d
U12
DSPI0_SCK
→
B68
PA13_DSPI0_SCK
+VREF3
t.b.d
U10
DSPI1_SCK
→
B74
PA08_DSPI1_SCK
+VREF3
t.b.d
B8
DSPI5_SCK
→
B79
PA09_DSPI5_SCK
+VREF3
t.b.d
E7
I2C0_SCL
→
B133
PB01_I2C0_SCL
+VREF3
PU: 2k7
400 kHz
C6
I2C1_SCL
→
B135
PB03_I2C1_SCL
+VREF3
PU: 4k7
400 kHz
A6
I2C2_SCL
→
B137
PB05_I2C2_SCL
+VREF3
PU: 4k7
400 kHz
AC13
CLKOUT_P
→
T82
CLK_OUT_P
+VREF1
SR: 0R
AB13
CLKOUT_N
→
T81
CLK_OUT_N
+VREF1
SR: 0R
AC11
AUR_CLK_P
←
T97
AUR_CLK_P
+VREF1
t.b.d.
AB11
AUR_CLK_N
←
T96
AUR_CLK_N
+VREF1
t.b.d.
W9
TCK
←
B82
JTAG_TCK
+VREF3
PD: 10k
t.b.d.
V20
RGMII0_TX_
CLK
→
T67
RGMII0_TX_
CLK
+VREF1
SR: 10R
125 MHz
V21
RGMII0_RX_
CLK
←
T59
RGMII0_RX_
CLK
+VREF1
SR: 10R
125 MHz
Y21
RGMII0_MDC
→
T50
RGMII0_MDC
+VREF1
SR: 10R
< 10 MHz.
P20
RGMII1_TX_
CLK
→
T48
RGMII1_TX_
CLK
+VREF1
SR: 10R
125 MHz
R21
RGMII1_RX_
CLK
←
T40
RGMII1_RX_
CLK
+VREF1
SR: 10R
125 MHz
V23
RGMII1_MDC
→
T31
RGMII1_MDC
+VREF1
SR: 10R
< 10 MHz
N19
RGMII2_TX_
CLK
→
T29
RGMII2_TX_
CLK
+VREF2
SR: 10R
125 MHz
P21
RGMII2_RX_
CLK
←
T21
RGMII2_RX_
CLK
+VREF2
SR: 10R
125 MHz
M19
RGMII2_MDC
→
T12
RGMII2_MDC
+VREF2
SR: 10R
< 10 MHz
Table 12 Clock: pin assignments