VSC8514 Evaluation Board
VPPD-03695 VSC8514 User Guide Revision 1.0
3
3
General Description
The evaluation board, shown in Figure 1, provides the user a way to evaluate the VSC8514 device in
multiple configurations. Four RJ-45 connectors are provided for copper media interfaces. The MAC
interface is exposed via SMA connectors.
For access to all of the features of the device, an external microcontroller is used to configure the on-
board clock chip via a two wire serial bus and the VSC8514 via the MDIO bus. The GUI enables the user
to read and write device registers.
3.1
Key Features
3.1.1
Copper Port RJ45 Connections
PHY ports 2 and 3 use the UDE RTA 1648BAK1A with integrated magnetic while PHY ports 0 and 1 use
generic RJ45 connectors with discrete Pulse H5008NL magnetics.
SGMII/QSGMII MAC SMA
The QSGMII differential input port is available through SMA connectors J1 and J2, while the output port
is available through SMA connectors J4 and J5. Both of them are AC coupled.
Switch Block Control
SW1 controls COMA_MODE, CLK_SQUELCH_IN and REFCLKSEL_[1:0]. The default configuration is with
all switches set to low as shown in the figure below.
Figure 2 • SW1 Switch Control
3.1.2
Zarlink ZL30343 SyncE G.8262/SETS
The Silabs F311 micro-controller is pre-programmed to configure the Zarlink ZL30343 to provide a 125
MHz differential LVPECL clock to the VSC8514 REFCLK input, either based on the 20 MHz on-board
crystal, or RCVRDCLK1 from the VSC8514 (Sync-E mode). When RCVRDCLK1 is enabled to output a
proper 125 MHz clock, the ZL30343 will generate a 125 MHz output clock synchronized to the
RCVRDCLK1 and will switch from HOLDOVER mode to LOCK mode as indicated by LEDs D33 and D34 as
shown in the figure below.
The left side of the illustration shows the HoldOver mode and the right side shows the Lock mode.
