Key Components Description and Operation
UG0557 User Guide Revision 4.0
17
4.4.4
SERDES3 Interface
The SERDES3 lanes are connected as follows.
•
Lane 0 is connected to the FMC connector.
•
Lane 1 is connected to the SMA connectors.
•
Lanes 2 and 3 are connected to the Marvell PHY device ports 0 and 1, respectively.
•
SERDES3 reference clock 0 is connected from FMC connector or SMA connector through MUX.
•
SERDES3 reference clock 1 is connected from 125 MHz or 100 MHz through MUX.
The following figure shows the SERDES3 interface of the SmartFusion2 Advanced Development Board.
Figure 10 • SERDES3 Interface
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