Microsemi LX7720, Руководство пользователя

Страница: 16 / 31

LX7720 Daughter Board User's Manual
June 2020 LX7720 Daughter Board rev 2.1 16
© 2020 Microsemi Corporation
4.13 Resolver/LVDT Interface
Links J5 to J8 configure the resolver/LVDT driver outputs with or without LC filtering for primary drive wave shaping.
Link J5 is left open by default to set LX7720 DMOD_BW pin 114 = low, selecting the longer DMOD_OUT_N pin 44 and
DMOD_OUT_P pin 46 driver propagation delay. To select the shorter driver propagation delay, set LX7720 DMOD_BW
pin 114 = high by connecting J5 pin 1 to VDD. Nearby VDD points include J38 pin 1 and J40 pin 1.
Standard connections for the
resolver used to develop the RTG4 programming are:
•
Links J5 to J8: all open
•
Primary: J13 pin 1: black/white, J13 pin 2: n/c, J13 pin 3: red/white
•
Secondary 1: J14 pin 3: red, J14 pin 4: black
•
Secondary 2: J14 pin 5: blue, J14 pin 6: yellow
Table 13. Resolver/LVDT Link Settings
Resolver/LVDT Options J6 Link J7 Link J8 Link J14 Connector J13 Connector
Resolver/LVDT driver outputs DMOD_OUT_P and
DMOD_OUT_N routed directly to J13 without filtering
Open
DMOD_OUT_P: pin 1
DMOD_OUT_N: pin 3
Resolver/LVDT driver outputs DMOD_OUT_P and
DMOD_OUT_N routed to J13 with LC filtering. The filter
shapes the PWM output waveform
Link 1 to 2
Open Open
ADC1, ADC2,
and ADC3
available for
general use
Resolver/LVDT driver outputs DMOD_OUT_P and
DMOD_OUT_N routed to J13 with LC filtering. The filter
shapes the PWM output waveform. ADC_3 is used to
monitor the filtered drive output for closed loop control of
the drive amplitude and for fault detection
Link 1 to 2 Link 1 to 2 Link 1 to 2
Only ADC1 and
ADC2 available
for general use
DMOD_OUT_P: pin 2
DMOD_OUT_N: pin 3
Figure 20. Resolver/LVDT Driver and ADC1, ADC2, ADC3 Inputs and Sigma-Delta Modulator Outputs