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 Mercury 2 FPGA Module

 

 Reference Manual

 

 
 

 

www.micro-nova.com

 

 

 

 

 

 

 

 

 

v1.0 August 2, 2019 

© 2019 MicroNova LLC 

1 of 9

 

 

OVERVIEW 

 
Mercury 2 

is an ultra-compact 

3” x 1”

 Xilinx Artix-7 

FPGA development board. The convenient 64-pin 
DIP form-factor makes it easy to add an FPGA to a 
breadboard, protoboard, or to your own custom PCB 
design. The 

Mercury 2

 module provides a complete 

FPGA solution, encapsulating all the required power, 
configuration, and I/O circuitry, leaving you to focus 
on your project. 

 

 
Unlike most FPGA development boards, 

Mercury 2 

is 

equipped with 5V tolerance on 40 digital I/O pins, so 
FPGA logic can be safely and easily interfaced with 
5V logic level devices. The 

Mercury 2

 board also 

supports a wide range of analog I/O, including an  
8-channel SPI ADC with external VREF up to 5V,  
a 2-channel SPI DAC, and the 1-MSPS Xilinx XADC. 
An external 4Mbit SRAM provides a high-speed 
buffer for data acquisition and signal processing. 

Mercury 2

 has a 32 Mb SPI flash to hold the FPGA 

bitstream and user data. The board has a micro USB 
port for easy programming and user data transfer. 
The board is also equipped with a 10/100 Ethernet 
PHY for network connectivity. 

The complete schematics for 

Mercury 2

 are 

available on our website, along with open-source 
USB programmer apps for Windows and Linux, and 
several example projects, and reference designs.

 

 

SPECIFICATIONS 
 

 

Xilinx Artix-7 FPGA (XC7A35T-1FTG256C) 

 

33,280 logic cells 

 

1,800 Kbits internal block RAM 

 

90 DSP slices (DSP48E1 48-bit ALUs) 

 

5 clock management tiles (CMT)

 

 

 

FTDI FT2232H dual-channel 480Mbps  
USB 2.0 interface with Micro-USB port 

 

Channel A: FPGA configuration and debug 

 

Channel B: user-configurable interface  
for high-speed data transfer

 

 

 

32 Mbit SPI flash

 (up to 16.7 Mbit used for 

FPGA bitstream, remainder for user data)

 

 

 

4 Mbit SRAM 

(512 K x 8 bit) with  

fast, asynchronous 10 ns interface 

 

 

50MHz MEMS oscillator

 (±50 ppm)

 

 

 

Digital input/output 

 

40x 5V tolerant digital I/O pins

 (SN74CB3T)

 

 

10x FPGA-direct I/O pins 

 

3x user LEDs 
 

 

Analog input/output

 

 

8-channel, 200 KSPS 10-bit ADC 

(MCP3008)

 

 

2-channel, 220 KSPS 10-bit DAC 

(MCP4812)

 

 

1 MSPS 12-bit Xilinx XADC module 

 

(1x direct input and 3x AUX inputs)

 

 

 

Network communications 

 

10/100 Ethernet PHY

 (Microchip LAN8720A) 

for use with Ethernet jack breakout board

 

 

Expansion header

 

(1x8 pin, 0.05”) 

intended 

for use with the ESP-11 Wi-Fi module 

 

Figure 1:

 

Mercury 2 FPGA Module

 

Содержание Mercury 2

Страница 1: ...er The board is also equipped with a 10 100 Ethernet PHY for network connectivity The complete schematics for Mercury 2 are available on our website along with open source USB programmer apps for Wind...

Страница 2: ...Mercury 2 Reference Manual v1 0 August 2 2019 2019 MicroNova LLC www micro nova com 2 of 9 Figure 2 Simplified Block Diagram Figure 3 DIP Pin Distribution...

Страница 3: ...Programming status LED RED 5 D1 Power LED GREEN 6 Optional ESP8266 ESP 11 Wi Fi Module header connection 7 Xilinx XADC Analog Input Connection 8 Optional JTAG header See Configuration section for det...

Страница 4: ...ation CONFIGURATION At power on the Artix 7 FPGA must be configured before it can perform any useful function The FPGA is essentially a blank slate of memory cells and programmable circuit interconnec...

Страница 5: ...e SPI Flash or erasing the entire SPI Flash Before accessing the SPI Flash the FT2232H asserts the FPGA_PROG pin during which time the FPGA is kept in reset and prevented from reading from the SPI Fla...

Страница 6: ...interfacing with 5V logic consider whether the device requires 5V CMOS logic levels or 5V TTL logic levels The level shifting logic onboard Mercury 2 is made to handle 5V inputs However Mercury s I O...

Страница 7: ...default configuration of Mercury 2 uses a 4Mbit SRAM part ISSI IS61WV5128BLL 10TLI but 8Mbit and 16Mbit SRAM modules are available as a build to order option Note that the upper address bits A 20 19...

Страница 8: ...ther channel can be driven by a range of inputs including the direct coax input as well as aux inputs on direct I O pins 3 8 The XADC can also be used to monitor the FPGA internal temperature and powe...

Страница 9: ...C driver and sine wave generator project ETHERNET PHY Mercury 2 includes a SMSC LAN8720A 10 100 Ethernet PHY 0 1 header holes are provided on Mercury 2 for connecting an optional RJ 45 Ethernet jack w...

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