Microchip Technology PIC24FV16KM204 FAMILY, Техническое описание

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PIC24FV16KM204 FAMILY
DS33030A-page 82
Advance Information
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2013 Microchip Technology Inc.
7.1 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in
Table 7-2 . If clock
switching is disabled, the system clock source is always
selected according to the Oscillator Configuration bits.
For more information, see
Section 9.0 “Oscillator
Configuration” .
TABLE 7-2: OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
7.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in
Table 7-3 . Note that the system Reset
signal, SYSRST, is released after the POR and PWRT
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
TABLE 7-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type Clock Source Determinant
POR FNOSCx Configuration bits
(FNOSC<10:8>)
BOR
MCLR COSCx Control bits
(OSCCON<14:12>)
WDTO
SWR
Reset Type Clock Source SYSRST Delay
System Clock
Delay
Notes
POR
( 6 )
EC T
POR
+ T
PWRT
— 1 , 2
FRC, FRCDIV T
POR
+ T
PWRT
T
FRC
1 , 2 , 3
LPRC T
POR
+ T
PWRT
T
LPRC
1 , 2 , 3
ECPLL T
POR
+ T
PWRT
T
LOCK
1 , 2 , 4
FRCPLL T
POR
+ T
PWRT
T
FRC
+ T
LOCK
1 , 2 , 3 , 4
XT, HS, SOSC T
POR
+ T
PWRT
T
OST
1 , 2 , 5
XTPLL, HSPLL T
POR
+ T
PWRT
T
OST
+ T
LOCK
1 , 2 , 4 , 5
BOR EC T
PWRT
— 2
FRC, FRCDIV T
PWRT
T
FRC
2 , 3
LPRC T
PWRT
T
LPRC
2 , 3
ECPLL T
PWRT
T
LOCK
2 , 4
FRCPLL T
PWRT
T
FRC
+ T
LOCK
2 , 3 , 4
XT, HS, SOSC T
PWRT
T
OST
2 , 5
XTPLL, HSPLL T
PWRT
T
FRC
+ T
LOCK
2 , 3 , 4
All Others Any Clock — — None
Note 1: T
POR
= Power-on Reset delay.
2: T
PWRT
= 64 ms nominal if the Power-up Timer is enabled; otherwise, it is zero.
3: T
FRC
and T
LPRC
= RC oscillator start-up times.
4: T
LOCK
= PLL lock time.
5: T
OST
= Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.
6: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC,
and in such cases, FRC start-up time is valid.
Note: For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics” .