Microchip Technology Microsemi PolarFire, Демонстрационное руководство

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Libero Design Flow
Microsemi Proprietary DG0799 Demo Guide Revision 3.0 18
3.1 Synthesize
To synthesize the design:
1. On the Design Flow tab, double-click Synthesize .
When the synthesis is successful, a green tick mark appears next to Synthesize , as shown in
Figure 16, page 17.
2. Right-click Synthesize and select View Report to view the synthesis report and log files in the
Reports tab.
We recommend viewing the
top.srr
and
top_compile_netlist.log
files for debugging syn-
thesis and compile errors.
3.2 Place and Route
The demo project includes the IO PDC file and the floor planner PDC constraint files. The Place and
Route process uses these PDC files to place the I/Os and CCC macros.
To place and route the design:
1. On the Design Flow tab, double-click Place and Route .
When place and route is successful, a green tick mark appears next to Place and Route , as shown
in Figure 16, page 17.
2. Right-click Place and Route and select View Report to view the place and route report and the log
files in the Reports tab.
We recommend viewing the
top_place_and_route_constraint_coverage.xml
file for
place and route constraint coverage.
3.2.1 PLL, DLL, and Lane Controller Placement
PolarFire FPGA I/O pairs are grouped into lanes. Each I/O bank has multiple lanes. Each lane consists of
twelve I/Os (six I/O pairs), a lane controller, and a set of high-speed, low-skew clock resources.
All associated I/Os must be placed in one lane. For example, RX_P and RX_N must be placed in the
same lane. For more information, see
UG0686: PolarFire FPGA User I/O User Guide . The IO Editor
shows the placement of the components and I/Os. The PLL of PF_CCC and the PLL, DLL, and Lane
Controller of PF_IOD_CDR_CCC_C0 are auto placed by Libero SoC.
3.2.2 Resource Utilization
The resource utilization report is written to the
top_layout_log.log
file in the Reports tab under
iog_cdr_1Gbps reports > Place and Route. Table 3, page 18 lists the resource utilization of the design
after place and route. These values may vary slightly for different Libero runs, settings, and seed values.
3.3 Verify Timing
To verify timing:
Table 3 • Resource Utilization
Type Used Total Percentage
4LUT 22551 299544 7.53
DFF 12703 299544 4.24
I/O register 0 510 0.00
Logic Elements 24090 299544 8.04
User I/O 21 512 4.10
– Single-ended I/O 17 512 3.32
– Differential I/O pairs 3 256 1.17