PolarFire FPGA 1G Ethernet Loopback Using IOD CDR
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
13
Figure 12 •
CoreAHBLite_0 Configuration
2.3.3.14 CoreAHBLite_2
CoreAHBLite_2 is configured as shown in
page 14 to interface the APB peripherals to the Mi-
V processor at 0x6000_0000.