PolarFire FPGA 1G Ethernet Loopback Using IOD CDR
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
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2.3.3.10 CORESPI_0
The CORESPI_0 (CoreSPI) block is a controller IP, which implements SPI communication. Mi-V
configures the ZL30364 clock generation hardware using the CORESPI_0 block. The following points
describe the CoreSPI_0 configuration, as shown in
•
APB Data Width is selected as 32 because the design uses an APB data width of 32 bit.
•
The default serial protocol mode, Motorola mode is retained to interface with ZL30364.
•
Frame size is set to 16 to match the read/write cycles supported by ZL30364.
•
FIFO depth is set to 32 to store maximum frames (TX and RX) in FIFO.
•
Clock rate for the SPI master clock is selected as 7. This is used to generate the SPI clock of 5 MHz
(SPICLK = PCLK/(2*(clock rate+1) = 80/(2*(7+1)) = 5 MHz).
•
The
Keep SSEL active
check box is enabled to keep the slave peripheral active between back-to-
back data transfers.
page 11 shows the CoreSPI configuration.
Figure 10 •
CoreSPI_0 Configurator
2.3.3.11 CoreUARTapb_0
The CoreUARTapb_0 block is a serial communication controller with a flexible serial data interface. It is
used for UART communication between the device and host PC. This IP retains the default configuration.
