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Microchip Technology Microsemi HDMI TX IP, Руководство пользователя

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Revision History

Microsemi Proprietary and Confidential UG0862 User Guide Revision 1.0

1

1

Revision History

The revision history describes the changes that were implemented in the document. The changes are 

listed by revision, starting with the most current publication.

1.1

Revision 1.0

This is the first publication of this document.

Содержание Microsemi HDMI TX IP

Страница 1: ...UG0862 User Guide HDMI TX...

Страница 2: ...i It is the Buyer s responsibility to independently determine suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided as is where is and...

Страница 3: ...de Revision 1 0 i Contents 1 Revision History 1 1 1 Revision 1 0 1 2 Introduction 2 3 Hardware Implementation 3 4 Inputs and Outputs 4 4 1 Ports 4 4 2 Configuration Parameters 4 4 3 Testbench Simulati...

Страница 4: ...Testbench 5 Figure 4 HDMI TX in Libero SoC Catalog 5 Figure 5 Parameter Configuration 6 Figure 6 Promote to Top Level 6 Figure 7 Generate Component 6 Figure 8 Simulating Testbench 7 Figure 9 ModelSim...

Страница 5: ...er Guide Revision 1 0 iii Tables Table 1 Inputs and Outputs 4 Table 2 Configuration Parameters 4 Table 3 Testbench Configuration Parameter 4 Table 4 Resource Utilization for 1 Pixel Per Clock 8 Table...

Страница 6: ...er Guide Revision 1 0 1 1 Revision History The revision history describes the changes that were implemented in the document The changes are listed by revision starting with the most current publicatio...

Страница 7: ...ng serial data at a high speed while minimizing potential for EMI Electro Magnetic Interference over copper cables by minimizing the number of transitions reducing interference between channels achiev...

Страница 8: ...ontrol data hsync and vsync is encoded to 10 bits in 4 possible combinations to help the receiver synchronize its clock with the transmitter clock A Transceiver should be used along with the HDMI TX I...

Страница 9: ...lly the same clock as the display controller RESET_N_I Input 1 bit Asynchronous active low reset signal DATA_VALID_I Input 1 bit Data valid input 1 for video data 0 for control data H_SYNC_I Input 1 b...

Страница 10: ...Figure 3 Naming SmartDesign Testbench SmartDesign testbench is created and a canvas appears to the right of the Design Flow pane 4 In the Libero SoC Catalog View Windows Catalog expand Solutions Video...

Страница 11: ...ht click and select Promote to Top Level as shown in the following figure Figure 6 Promote to Top Level 7 Click Generate Component from the SmartDesign toolbar as shown in the following figure Figure...

Страница 12: ...Simulating Testbench The ModelSim tool appears with the test bench file loaded on to it as shown in the following figure Figure 9 ModelSim Tool with HDMI TX Testbench File If the simulation is interru...

Страница 13: ...s of control data Figure 11 HDMI TX IP Timing Diagram of Control Data for 1 Pixel Per Clock 4 5 Resource Utilization HDMI TX IP is implemented in PolarFire FPGA MPF300T 1FCG1152I Package The following...

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