Microchip Technology MCP651, Руководство пользователя

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MCP651 INPUT OFFSET
EVALUATION BOARD
USER’S GUIDE
©
2009 Microchip Technology Inc. DS51834A-page 25
Appendix A. Schematics and Layouts
A.1 INTRODUCTION
This appendix contains the schematics and layouts for the MCP651 Input Offset
Evaluation Board.
A.2 SCHEMATIC AND LAYOUTS
See A.3 “Board – Schematic” for the circuit diagram. U1 is the DUT (MCP651). U2
buffers the attenuated and filtered control voltage VCOX. U3 is the differential
integrator. U4 is the amplifier that gives the final gain to the DUT’s input offset voltage
(V
OST
). Switch S1 gives the user a means of starting an auto-calibration cycle in the
DUT. Switch S2 makes it so the amplifier (U4) can have two different gains, providing
a tradeoff between accuracy and range.
A.4 “Board – Combination of the Top Silk-Screen, Top Solder Mask and Top Metal
Layers”
through A.7 “Board – Bottom Metal Layer” show the PCB layout plots. This
PCB has two metal layers: signal and power traces on top and ground plane on bottom.
Groups of critical resistors have been arranged so that their thermoelectric voltages
cancel (assuming constant temperature gradient); these groups are:
• R
1
through R
4
• R
5
and R
6
• R
7
and R
8
• R
21
through R
23
• R
24
and R
25
The Gerber files for this board are available on the Microchip website
(www.microchip.com) and are contained in the zip file “
00258R2_Gerbers.zip
”.