Installation and Operation
2020 Microchip Technology Inc.
DS50003006A-page 19
2.4
INTERFACE CONNECTIONS
TABLE 2-3:
J2 CONTROL INTERFACE SIGNALS
Pin No.
Name
Test Point
I/O Type
Signal Direction
J2-A2
SCK
—
LVCMOS-2.5V Input
EEPROM Serial Clock Input
J2-B2
CSB
—
LVCMOS-2.5V Input
EEPROM Chip Select Input
J2-A3
MISO
—
LVCMOS-2.5V Output EEPROM Serial Data Output
J2-B3
MOSI
—
LVCMOS-2.5V Input
EEPROM Serial Data input
J2-A5
CLR
T2
LVCMOS-3.3V Input
HV2918 Latch Clear Logic Input
J2-B5
CLK
T4
LVCMOS-3.3V Input
HV2918 Clock Logic Input
J2-C5
LE
T1
LVCMOS-3.3V Input
HV2918 Latch Enable Logic Input
J2-A6
DIN
T3
LVCMOS-3.3V Input
HV2918 Data In Logic Input
J2-C6
A1
T33_P2
LVCMOS-3.3V Input
Ch1 Pulser input for NMOS to V
NN
J2-D6
B1
T34_P2
LVCMOS-3.3V Input
Ch1 Pulser input for PMOS to V
PP
J2-A7
DMP1
T35_P2
LVCMOS-3.3V Input
Ch1 Pulser Damp Input for PMOS/NMOS to GND
J2-B7
A2
T33_P1
LVCMOS-3.3V Input
Ch2 Pulser input for NMOS to V
NN
J2-C7
B2
T34_P1
LVCMOS-3.3V Input
Ch2 Pulser input for PMOS to V
PP
J2-D7
DMP2
T35_P1
LVCMOS-3.3V Input
Ch2 Pulser Damp Input for PMOS/NMOS to GND
Содержание HV2918
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