EVB-USB3503 QFN
EVALUATION BOARD
USER’S GUIDE
2014 Microchip Technology Inc.
DS50002252A-page 9
Chapter 1. Overview
1.1
EVB-USB3503 QFN OVERVIEW AND FEATURES
The USB3503 is a low-power, full-featured and OEM configurable Multi-Transaction
Translator (MTT) USB 2.0 hub controller with three downstream ports optimized for
portable applications. The USB3503 is fully compliant with the USB 2.0 Specification,
High-Speed Inter-Chip (HSIC) USB Electrical Specification Revision 1.0 and attaches
to an upstream port as a high-speed hub. The 3-port hub supports low-speed,
full-speed and high-speed downstream devices on all of the enabled downstream
ports. The upstream HSIC port supports only high-speed operation. The
EVB-USB3505 QFN Evaluation Board demonstrates a stand-alone application for the
USB3503 device. See
for additional information.
1.2
FEATURES
• USB3503 in a 32-pin QFN RoHS compliant package
• One upstream HSIC port
• Three USB 2.0 downstream ports with ganged port power and overcurrent sense
(OCS)
• High-Speed (480 Mbps), Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps)
compatible on downstream USB ports
• Multi-Transaction Translator is enabled
• Supports internal default hub configuration. Optionally supports external
configuration via I
2
C
• I
2
C interface header available
• Self-Powered operation
• Operates from one single voltage (+5.0 VDC, 4 Amp regulated) external power
supply
• On Board +3.3 VDC and +1.8 VDC regulators
• Interrupt LED indicator
• Single 26 MHz oscillator clock source
• Schematics, layout and bill of materials are available to minimize new product
development time
1.3
GENERAL DESCRIPTION
The EVB-USB3503 QFN is an evaluation and demonstration platform featuring the
USB3503 Ultra Fast USB 2.0 Hub on an RoHS compliant Printed Circuit Board (PCB).
The EVB-USB3503 QFN is designed to demonstrate the unique features of this device
using a low-cost PCB implementation with ganged port power control for the three
downstream USB 2.0 ports.
The EVB-USB3503 QFN is designed to support internal default configuration settings
or external configuration through I
2
C via the SDA and SCL header pins.
details the top and bottom level silk screen and copper layers. A block diagram of the
evaluation board can be seen in
