Getting Ready for Development
2022 Microchip Technology Inc. and its subsidiaries
DS50003324A-page 21
7.1
EVALUATING CEC1736 WITH USER'S SYSTEM
Users may consider connecting the CEC1736 Development Board to the system for
further evaluation and product development.
The CEC1736 development board has designed the way that we can disable the
MEC1723 by changing the followings:
• Remove J65 to disconnect the CEC1736 AP0_RESET# to MEC1723 RESET_IN#
pin
• Jumper the J43 and J44 to hold the MEC1723 in reset, and all the connected pins
will be at input mode and tri-stated.
• Connect P4 (BMC Host Header) to the Platform AP0 interface
- CEC1736 QSPI0_IN bus to AP0 QMSPI bus
- CEC1736 AP0_RESET# to the AP0 reset pin
- CEC1736 I2C channel to AP0 I2C channel
- Other optional feature signals that required in the design
• If dual channels are used, connect P5 (CPU Host Header) to the Platform AP1
interface
- CEC1736 QSPI1_IN bus to AP1 QMSPI bus
- CEC1736 AP1_RESET# to the AP1 reset pin
- Other optional feature signals that required in the design
