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dsPIC30F Quadrature Encoder Interface Module
© 2005 Microchip Technology Inc.
Page 6
© 2005 Microchip Technology Incorporated. All Rights Reserved.
dsPIC30F Quadrature Encoder Interface Module
6
Block Diagram
Clock
Divider
INDEX
1
0
TQCS
Tcy
Digital Filter
Logic
Digital Filter
Logic
Digital Filter
Logic
QEB
QEA
Prescaler and
Sync. Logic
Tcy
UPDN
16-Bit Up/Down
Counter
DIR
Quadrature
Decoder
Logic
Clock
Reset
Max. Count
Register
Timer Mode
Timer Mode
Comparator
This block diagram depicts the internal architecture of the QEI modules. We
can see the input pins and the associated digital filters. There is also an
up/down input pin that is mainly used when the unit operates as a counter. The
quadratrute decoder logic is responsible for analysing which edge comes first
and the counter accumulates the edge count and is compared with the internal
Max Count Register.